Philips 74alvt16823 DATASHEETS

INTEGRATED CIRCUITS

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable (3-State)

Product specification Supersedes data of 1998 Mar 03 IC23 Data Handbook

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1998 Jun 12

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset and enable (3-State)

FEA TURES

•Two sets of high speed parallel registers with positive

edge-triggered D-type flip-flops

•5V I/O Compatible

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up Reset

•No bus current loading when output is tied to 5 V bus

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Bus hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

DESCRIPTION

The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

The 74ALVT16823 has two 9-bit wide buffered registers with Clock Enable (nCE interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

It is designed for V compatibility to 5 V .

74AL VT16823

) and Master Reset (nMR) which are ideal for parity bus

operation from 2.5 V to 3.0 V with I/O

QUICK REFERENCE DATA

TYPICAL

2.5V 3.3V

3 3 pF

PLH

PHL

OUT

CCZ

CONDITIONS

= 25°C; GND = 0V

amb

Propagation delay nCP to nQx

Input capacitance VI = 0V or V Output capacitance V Total supply current Outputs disabled 40 70 µA

CL = 50pF 2.5 1.9 ns

= 0V or 3.0V 9 9 pF

I/O

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16823 DL AV16823 DL SOT371–1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16823 DGG AV16823 DGG SOT364–1

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

2, 27 1OE, 2OE Output enable input (active-Low)

54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31

3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26

56, 29 1CP, 2CP Clock pulse input (active rising edge) 55, 30 1CE, 2CE Clock enable input (active-Low)

1, 28 1MR, 2MR Master reset input (active-Low)

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

1D0-1D8 2D0-2D8

1Q0-1Q8 2Q0-2Q8

Data inputs

Data outputs

Positive supply voltage

1998 Jun 12 853-2069 19558

Philips Semiconductors Product specification

2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset and enable (3-State)

PIN CONFIGURATION

1 2

1OE

1Q0

GND

1Q1

1Q2

1Q3

1Q4

1Q5

GND

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

2Q6

2Q7

GND

2Q8

2OE

28 29

2MR

561MR

1CP

1CE

1D0 GND

1D1

1D2

1D3

1D4

1D5

GND

1D6

1D7

1D8

2D0

2D1

2D2

GND

2D3

2D4

2D5

2D6

2D7

GND

2D8

2CE 2CP

LOGIC SYMBOL (IEEE/IEC)

1OE 1MR

1CE

1CP 2OE 2MR

2CE

2CP

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

1 55 56 27 28 30 29

54 52 51 49 48 47 45 44 43 42

41 40 38 37 36 34 33 31

EN1 R2 G3

3C4 EN5 R6 G7

7C8

74ALVT16823

1, 2 ∇

5, 6 ∇

3 5 6 8

9 10 12 13 14 15 16 17 19 20 21 23 24 25

SH00015

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8

LOGIC DIAGRAM

nCE

nCP

nMR

nOE

n = 1 or 2

1998 Jun 12

SH00014

nD0

nD1

CP CP CP CP CP CP CP CP CP

nQ0

nD2

Q Q Q Q Q Q Q Q

nQ1

nD3

nQ2

nQ3

nD4

nD5

nQ4

nQ5

nD6

nD7

nQ6

nQ7

nD8

nQ8

SH00016

Philips Semiconductors Product specification

OPERATING MODE

Load and read data

DC output current

2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset and enable (3-State)

FUNCTION TABLE

INPUTS OUTPUTS

nOE nMR nCE nCP nDx nQ0 – nQ8

L L X X X L Clear L H L ↑ h H L H L ↑ l L L H H ↑ X NC Hold H X X X X Z High impedance

H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

74ALVT16823

Data Input

ABSOLUTE MAXIMUM RATINGS

SYMBOL

OUT

stg

DC supply voltage -0.5 to +4.6 V DC input diode current VI < 0 -50 mA DC input voltage DC output diode current VO < 0 -50 mA DC output voltage

Storage temperature range -65 to +150 °C

PARAMETER CONDITIONS RATING UNIT

To internal circuit

SW00044

1, 2

-0.5 to +7.0 V

Output in Off or High state -0.5 to +7.0 V

Output in Low state 128

Output in High state -64

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

1998 Jun 12

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