Philips 74ALVT16501DL, 74ALVT16501DGG Datasheet

INTEGRATED CIRCUITS
74ALVT16501
2.5V/3.3V 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1997 May 01 IC23 Data Handbook
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
2.5V/3.3V 18-bit universal bus transceiver (3-State)
FEA TURES
18-bit bidirectional bus interface
5V I/O Compatible
3-State buffers
Output capability: +64mA/-32mA
TTL and LVTTL input and output switching levels
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Positive edge triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 400V per Machine Model
QUICK REFERENCE DATA
t
PLH
t
PHL
C C I
CCZ
IN
I/O
Propagation delay An to Bn or Bn to An
Input capacitance (Control pins) VI = 0V or V I/O pin capacitance V Total supply current Outputs disabled 40 60 µA
CL = 50pF
DESCRIPTION
The 74ALVT16501 is a high-performance BiCMOS product designed for V up to 5V .
This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CP AB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
CONDITIONS
T
amb
CC
= 0V or V
I/O
CC
CC
), latch enable (LEAB and LEBA), and clock (CPAB and
= 25°C
74AL VT16501
operation at 2.5V and 3.3V with I/O compatibility
,
TYPICAL
2.5V 3.3V
1.9
2.5 4 4 pF 8 8 pF
1.4
1.8
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16501 DL AV16501 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16501 DGG A V16501 DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OEAB A-to-B Output enable input
27 OEBA B-to-A Output enable input (active low)
2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input
55,30 CPAB/CPBA A-to-B/B-to-A Clock input (active rising edge)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
4, 11, 18, 25, 32, 39, 46, 53, 29, 56 GND Ground (0V)
7, 22, 35, 50 V
A0-A17 Data inputs/outputs (A side)
B0-B17 Data inputs/outputs (B side)
CC
Positive supply voltage
1998 Feb 13 853-1884 18958
2
Philips Semiconductors Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
PIN CONFIGURA TION
OEAB
1
LEAB
2
A0
3 4
GND
5
A1
6
A2
7
V
CC
8
A3
9
A4
10
A5
11
GND
12
A6
13
A7
14
A8
15
A9
16
A10
17
A11
18
GND GND
19
A12
20
A13
21
A14
22
V
CC
23
A15
24
A16
25
GND
26
A17
27
OEBA
28 29
LEBA
56
GND CPAB
55
B0
54 53
GND B1
52
B2
51 50
V
CC
49
B3
48
B4
47
B5
46
GND
45
B6
44
B7
43
B8
42
B9
41
B10
40
B11 39 38
B12 37
B13 36
B14 35
V
CC
34
B15 33
B16 32
GND 31
B17 30
CPBA
GND
LOGIC SYMBOL (IEEE/IEC)
OEAB CPAB LEAB
OEBA CPBA LEBA
A0
A1 A2 A3 A4
A5 A6 A7 A8
A9 A10 A11 A12 A13 A14 A15 A16 A17
74ALVT16501
1 55 2
27 30 28
3
5 6 8
9 10 12
13 14 15
16 17 19 20 21 23 24 26
EN1
2C3 C3 G2 EN4
5C6 C6 G5
3D 1 1 416D
54
B0
52
B1
51
B2
49
B3
48
B4
47
B5
45
B6
44
B7
43
B8
42
B9
41
B10
40
B11
38
B12
37
B13
36
B14
34
B15
33
B16
31
B17
LOGIC SYMBOL
54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
1998 Feb 13
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
CPBA
LEBA
OEBA
CPAB
LEAB
SA00128
1255272830
OEAB
A0 A1 A2 A3 A4 A5 A6 A7 A8
A9 A10 A11 A12 A13 A14 A15 A16 A17
SA00129
3 5 6 8
9 10 12 13 14 15 16 17 19 20 21 23 24 26
SW00026
3
Philips Semiconductors Product specification
Disabled, Latch data
Disabled, Clock data
Transparent
Latch data & displa
Clock data & displa
Hold data & displa
2.5V/3.3V 18-bit universal bus transceiver (3-State)
FUNCTION TABLE
INPUTS
OEAB LEAB CPAB An
L H X X X Z Disabled L X h H Z L X I L Z L L H or L X NC Z Disabled, Hold data L L h H Z
L L I L Z H H X H H H H H X L L L H X h H H H X I L L H L h H H H L I L L H L H or L X H H H L H or L X L L
NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level
h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock transition NC= No Change X = Don’t care Z = High Impedence ”off” state = High-to-Low Enable or Clock transition
Internal
Registers
OUTPUTS
Bn
OPERATING MODE
74ALVT16501
p
p
y
p
y
p
y
1998 Feb 13
4
Philips Semiconductors Product specification
2.5V/3.3V 18-bit universal bus transceiver (3-State)
LOGIC DIAGRAM
1
OEAB
28
LEBA
30
CPBA
55
CPAB
2
LEAB
27
OEBA
74ALVT16501
AO
C1
ID
3
1 of 18 channels
C1
ID
To 17 other channels
C1
ID
C1
ID
54
B0
SW00027
1998 Feb 13
5
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