Philips 74ALVT162245DL, 74ALVT162245DGG Datasheet

INTEGRATED CIRCUITS

74ALVT162245

2.5V/3.3V ALVT 16-bit transceiver with
30 termination resistors (3-State)

Product specification
Supersedes data of 1996 Mar 05
IC23 Data Handbook

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1998 Feb 13

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

2.5V/3.3V 16-bit transceiver

74AL VT162245

with 30Ω termination resistors (3-State)

FEA TURES

•16-bit bidirectional bus interface

•3-State buffers

•5V I/O compatibile

•Output capability: +12mA/-12mA

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Live insertion/extraction permitted

•Outputs include series resistance of 30Ω making external

termination resistors unnecessary

•Power-up 3-State

•No bus current loading when output is tied to 5V bus

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

t

PLH

t

PHL

C

IN

C

I/O

I

CCZ

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

48-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT162245 DL AV162245 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT162245 DGG AV162245 DGG SOT362-1

Propagation delay
nAx to nBx or nBx to nAx

CL = 50pF

Input capacitance DIR, OE VI = 0V or V
I/O pin capacitance V
Total supply current Outputs disabled 40 70 µA

DESCRIPTION

The 74ALVT162245 is a high-performance BiCMOS product
designed for V
to 5V .

This device is a 16-bit transceiver featuring non-inverting 3-State
bus compatible outputs in both send and receive directions. The
control function implementation minimizes external timing
requirements. The device features an Output Enable (nOE
easy cascading and a Direction (DIR) input for direction control.

The 74ALVT162245 is designed with 30Ω series resistance in both
the High and Low states of the output. This design reduces line
noise in applications such as memory address drivers, clock drivers,
and bus transceivers/transmitters.

CONDITIONS

T

amb

CC

= 0V or V

I/O

CC

operation at 2.5V or 3.3V with I/O compatibility up

CC

TYPICAL

= 25°C

2.5V 3.3V

2.9

2.4

2.3

2.0
3 3 pF
9 9 pF

) input for

ns

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1, 24 nDIR Direction control input

47, 46, 44, 43,
41, 40, 38, 37,
36, 35, 33, 32,

30, 29, 27, 26

nA0 – nA7 Data inputs/outputs (A side)

LOGIC SYMBOL

1

1DIR

47

1A0

46

1A1

24

2DIR

48

1OE

2

1B0

3

1B1

2A0

2A1

36

35

2, 3, 5, 6, 8, 9,
11, 12, 13, 14,
16, 17, 19, 20,

nB0 – nB7 Data inputs/outputs (B side)

22, 23

25, 48 nOE

4, 10, 15, 21, 28,

34, 39, 45

7, 18, 31, 42 V

GND Ground (0V)

CC

1998 Feb 13 853-1827 18959

Output enable input
(active-Low)

Positive supply voltage

2

44

1A2

43

1A3

41

1A4

40

1A5

38

1A6

37 12

1A7

5

1B2

6

1B3

8

1B4

9

1B5

11

1B6

1B7

33

2A2

32

2A3

30

2A4

29

2A5

27

2A6

26 23

2A7

SA00021

25

2OE

13

2B0

14

2B1

16

2B2

17

2B3

19

2B4

20

2B5

22

2B6

2B7

Philips Semiconductors Product specification

2.5V/3.3V 16-bit transceiver
with 30Ω termination resistors (3-State)

PIN CONFIGURA TION

48

1DIR

1B0
1B1

GND

1B2

1B3

V

1B4
1B5

GND

1B6
1B7
2B0
2B1

GND

2B2
2B3

V

2B4
2B5

GND

2B6
2B7

2DIR

1
2
3

4
5

6
7

CC

8

9
10
11
12
13
14
15
16
17
18

CC

19
20
21
22
23
24

1OE

47

1A0

46

1A1

45

GND

44

1A2

43

1A3

42

V

CC

41

1A4

40

1A5

39

GND

38

1A6

37

1A7

36

2A0

35

2A1

34

GND

33

2A2

32

2A3

31

V

CC

30

2A4

29

2A5

28

GND

27

2A6

26

2A7

25

2OE

LOGIC SYMBOL (IEEE/IEC)

48

1OE

1

1DIR

25

2OE

24

2DIR

47

1A0

46

1A1

44 5

1A2

43 6

1A3

41 8

1A4

40 9

1A5

38 11

1A6

37 12

1A7

36

2A0

35

2A1

33 16

2A2

32 17

2A3

30 19

2A4

29 20

2A5

27 22

2A6

26 23

2A7

G3
3 EN1 (BA)

3 EN2 (AB)

G3
3 EN1 (BA)

3 EN2 (AB)

∇ 1

∇ 1

74ALVT162245

2

1B0

2 ∇

3

1B1
1B2

1B3
1B4
1B5

1B6
1B7

13

2B0

2 ∇

14

2B1
2B2

2B3
2B4
2B5
2B6
2B7

SV00066

SW00061

SCHEMATIC OF EACH OUTPUT

V

CC

27Ω

27Ω

1998 Feb 13

V

CC

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS

nOE nDIR nAx nBx

L L nAx = nBx Inputs
L H Inputs nBx = nAx

H X Z Z

H =High voltage level
L =Low voltage level

X = Don’t care
Z =High Impedance “off” state

OUTPUT

SW00206

3