Philips 74ALVCH16843DL, 74ALVCH16843DGG Datasheet
74ALVCH16843
18-bit bus-interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Aug 04
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74AL VCH1684318-bit bus interface D-type latch (3-State)
2
1998 Aug 04 853–2108 019833
FEA TURES
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 24 mA at 3.0 V
•MULTIBYTE
TM
flow-through standard pin-out architecture
•Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
•All data inputs have bus hold
•Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR
),
preset (nPRE
) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE
is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE
input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1OE
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
GND
V
CC
GND
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
GND
2Q
3
2Q
4
2Q
5
V
CC
2Q
6
2Q
7
GND
2Q
8
2CLR
1D
0
GND
1D
1
1D
2
V
CC
1D
3
1D
4
1D
5
GND
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
GND
2D
3
2D
4
2D
5
V
CC
2D
6
2D
7
GND
2D
8
2LE
1PRE
1CLR
2OE
1LE
2PRE
SH00143
QUICK REFERENCE DA TA
GND = 0V; T
amb
= 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
nDn to nQn
VCC = 2.5V , CL = 30pF
VCC = 3.3V , CL = 50pF
2.2
2.1
ns
t
PHL/tPLH
Propagation delay
nLE to nQn
VCC = 2.5V , CL = 30pF
VCC = 3.3V , CL = 50pF
2.3
2.0
ns
C
I
Input capacitance 5.0 pF
p
p
p
1
transparent mode
Output enabled
Output disabled
17
3
p
CPDPower dissi ation ca acitance er buffer
V
I
=
GND to V
CC
1
Clocked mode
Output enabled
Output disabled
19
9
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
P
D
= CPD × V
CC
2
× fi + (CL × V
CC
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
f
o
= output frequency in MHz; VCC = supply voltage in V; (CL × V
CC
2
× fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
DRAWING
NUMBER
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVCH16843 DGG ACH16843 DGG SOT364-1
Philips Semiconductors Product specification
74AL VCH16843
18-bit bus interface D-type latch (3-State)
1998 Aug 04
3
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1CLR Clear input (active LOW)
2 1OE
Output enable input (active
LOW)
55 1PRE Preset input (active LOW)
56 1LE
Latch enable input (active
HIGH)
54, 52, 51, 49, 48,
47, 45, 44, 43
1D0 to 1D8 Data inputs
3, 5, 6, 8, 9,
10, 12, 13, 14
1Q0 to 1Q8 Data outputs
4, 11, 18, 25,
32, 39, 46, 53
GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage
27 2OE
Output enable input (active
LOW)
28 2CLR Clear input (active LOW)
29 2LE
Latch enable input (active
HIGH)
30 2PRE Preset input (active LOW)
42, 41, 40, 38, 37,
36, 34, 33, 31
2D0 to 2D8 Data inputs
15, 16, 17, 19, 20,
21, 23, 24, 26
2Q0 to 2Q8 Data outputs
FUNCTION TABLE
INPUTS OUTPUT
nPRE nCLR nOE LE D
X
Q
L X L X X H
H L L X X L
H H L H L L
H H L H H H
H H L H X Q
0
X X H H X Z
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
LOGIC SYMBOL
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
1D
0
1D
1
1D
2
1D
3
1D
4
1D
5
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
2Q
3
2Q
4
2Q
5
2Q
6
2Q
7
2D
8
2Q
8
1OE
1LE
2OE
2LE
256
27 29
SH00144
1CLR
1PRE
2CLR
2PRE
155
28 30
14
15
43
42
Philips Semiconductors Product specification
74AL VCH16843
18-bit bus interface D-type latch (3-State)
1998 Aug 04
4
LOGIC DIAGRAM
SH00146
nD
0
nQ
0
D
CLR
DPRE
LE
nCLR
nLE
nPRE
nOE
BUS HOLD CIRCUIT
To internal circuit
V
CC
Data Input
SW00044
LOGIC SYMBOL (IEEE/IEC)
2, 3, 4 ∇
6, 7, 8 ∇
30
28
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
27
EN4
1D
0
1D
1
1D
2
1D
3
1D
4
1D
5
1D
6
1D
7
1D
8
2D
0
2D
1
2D
2
2D
3
2D
4
2D
5
2D
6
2D
7
1Q
0
1Q
1
1Q
2
1Q
3
1Q
4
1Q
5
1Q
6
1Q
7
1Q
8
2Q
0
2Q
1
2Q
2
2Q
3
2Q
4
2Q
5
2Q
6
2Q
7
29
2LE
2CLR
2PRE
2OE
2D
8
2Q
8
EN8
SH00145
43
42
14
15
56
1
2
56
1LE
1CLR
1PRE
1OE
S2
S6
R7
C1
C5
R3
C1
C5
1D
5D
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