Philips 74ALVCH16841DL, 74ALVCH16841DGG Datasheet

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74ALVCH16841

20-bit bus interface D-type latch (3-State)

Product specification
IC24 Data Handbook

1998 Jul 27

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

74AL VCH1684120-bit bus interface D-type latch (3-State)

2

1998 Jul 27 853-2093 19785

FEA TURES

•Wide supply voltage range of 1.2V to 3.6V

•Complies with JEDEC standard no. 8-1A

•Wide supply voltage range of 1.2V to 3.6V

•CMOS low power consumption

•Direct interface with TTL levels

•MULTIBYTE

TM

flow-through standard pin-out architecture

•Low inductance multiple V

CC

and GND pins for minimum noise

and ground bounce

•Current drive ±24 mA at 3.0 V

•All inputs have bus hold circuitry

•Output drive capability 50Ω transmission lines @ 85°C

•3-State non-inverting outputs for bus oriented applications

DESCRIPTION

The 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.

When nOE

is LOW, the data in the registers appears at the outputs.

When nOE

is High the outputs are in High-impedance OFF state.

Operation of the nOE

input does not affect the state of the flip-flops.

The 74ALVCH16841 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.

PIN CONFIGURATION

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE

1Q0
1Q1

GND

1Q2
1Q3

1Q4
1Q5

GND

1Q6

1Q7
1Q8

2Q2

1Q9

V

CC

2Q3

V

CC

2Q1

2Q4

2Q8

2OE

2Q7

1LE
1D0
1D1

GND

1D2
1D3

1D4
1D5

2D0

1D6

1D7

2D1
2D2
GND

2D4

V

CC

2D5

V

CC

2D3

2D6

GND
2D8

2LE

2D7

SA00076

2Q0

GND

2Q5

28

27

26

25

49

50

51

52

53

54

55

56

2D9

1D9

1D8

GND

2Q9

GND

2Q6

QUICK REFERENCE DA TA

GND = 0V; T

amb

= 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

Propagation delay
nDn to nQ

n

VCC = 2.5V , CL = 30pF
VCC = 3.3V , CL = 50pF

2.5

2.4

ns

t

PHL/tPLH

Propagation delay
nLE to nQ

n

VCC = 2.5V , CL = 30pF
VCC = 3.3V , CL = 50pF

2.5

2.4

ns

C

I

Input capacitance 5.0 pF

p

p

p

1

Outputs enabled 19

p

CPDPower dissi ation ca acitance er buffer

V

I

=

GND to V

CC

1

Outputs disabled 3

F

NOTES:

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

P

D

= CPD × V

CC

2

× fi +  (CL × V

CC

2

× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

f

o

= output frequency in MHz; VCC = supply voltage in V;  (CL × V

CC

2

× fo) = sum of outputs.

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16841 DGG ACH16841 DGG SOT364-1

Philips Semiconductors Product specification

74AL VCH1684120-bit bus interface D-type latch (3-State)

1998 Jul 27

3

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 1OE

Output enable inputs
(active-LOW)

56 1LE

Latch enable inputs
(active HIGH)

55, 54, 52, 51, 49,

48, 47, 45, 44, 43

1D0 – 1D9 Data inputs

2, 3, 5, 6, 8, 9, 10,

12, 13, 14

1Q0 – 1Q9 Data outputs

4, 11, 18, 25, 32,

39, 46, 53

GND Ground (0V)

7, 22, 35, 50 V

CC

Positive supply
voltage

28 2OE

Output enable inputs
(active-LOW)

29 2LE

Latch enable inputs
(active HIGH)

42, 41, 40, 38, 37,

36, 34, 33, 31, 30

2D0 – 2D9 Data inputs

15, 16, 17, 19, 20,

21, 23, 24, 26, 27

2Q0 – 2Q9 Data outputs

FUNCTION TABLE

INPUTS OUTPUT

nOE LE Dx Q

L H L L
L H H H
L L X Q

0

H X X Z

H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state

LOGIC SYMBOL

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

1D8 1D9

1Q8 1Q9

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

2D8 2D9

2Q8 2Q9

55 54 52 51 49 48 47 45 44 43

56

1

29
28

2 3 5 6 8 9 10 12 13 14

42 41 40 38 37 36 34 33 31 30

15 16 17 19 20 21 23 24 26 27

SH00023

1LE
1OE

2LE
2OE

LOGIC SYMBOL (IEEE/IEC)

1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7

1Q0
1Q1
1Q2

1Q3
1Q4
1Q5
1Q6
1Q7

1D8
1D9

1Q8

1Q9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7
2D8
2D9

2Q8

2Q9

EN4

2 ∇

EN2

4 ∇

1
56
28
29

55
54
52
51
49
48
47
45
44

43
42
41
40
38
37
36
34
33
31
30

2
3
5
6
8

9
10
12
13
14
15
16
17
19
20
21
23
24
26
27

1D

3D

C1

C3

1OE
1LE
2OE
2LE

SH00152

LOGIC DIAGRAM

nD

0

nQ

0

D

LE

nLE

nOE

SH00151