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INTEGRATED CIRCUITS
74ALVCH16825
18-bit buffer/driver (3-State)
Product specification
IC24 Data Handbook
1998 Jul 27
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Philips Semiconductors Product specification
CPDPower dissi ation ca acitance er latch
74AL VCH1682518-bit buffer/driver (3-State)
FEA TURES
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 24 mA at 3.0 V
•MULTIBYTE
•Low inductance multiple V
and ground bounce
TM
flow-through standard pin-out architecture
and GND pins for minimum noise
CC
•All data inputs have bus hold
•Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16825 is an 18–bit non-inverting buf fer/driver with
3-State outputs for bus-oriented applications.
The 74ALVCH16825 consists of two 9-bit sections with separate
output enable signals. For either 9-bit buffer section, the two output
enable (1OE
LOW for corresponding D outputs to be active. If either output
enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.
The 74ALVCH16825 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
PIN CONFIGURATION
1
2
1Y
1
3
1Y
1
4
GND
5
1Y
2
6
1Y
3
7
V
CC
8
1Y
4
9
1Y
5
1Y
10
6
GND
11
1Y
12
7
1Y
13
8
14
GND
15
GND
16
2Y
0
17
2Y
1
18
GND
19
2Y
2
20
2Y
3
21
2Y
4
22
V
CC
23
2Y
5
24
2Y
6
25
GND
26
2Y
7
27
2Y
8
28 29
2OE1
1OE
561OE1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
1A
1A
GND
1A
1A
V
CC
1A
1A
1A
GND
1A
1A
GND
GND
2A
2A
GND
2A
2A
2A
V
CC
2A
2A
GND
2A
2A
2OE2
2
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
QUICK REFERENCE DA TA
GND = 0V; T
SYMBOL
t
PHL/tPLH
C
I
NOTES:
is used to determine the dynamic power dissipation (PD in µW):
1. C
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; (CL × V
f
o
= 25°C; tr = tf ≤ 2.5ns
amb
Propagation delay
CP to Qn
Input capacitance 4.0 pF
2
CC
ORDERING INFORMATION
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVCH16825 DGG ACH16825 DGG SOT364-1
1998 Jul 27 853-2097 19785
PARAMETER CONDITIONS TYPICAL UNIT
p
× fi + (CL × V
PACKAGES
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
p
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
CC
p
=
I
2
× fo) = sum of outputs.
CC
TEMPERATURE
CC
OUTSIDE NORTH
RANGE
Output enabled 19
Output disabled 3
AMERICA
2
SH00139
2.0
2.0
NORTH AMERICA
ns
p
DRAWING
NUMBER
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Philips Semiconductors Product specification
18-bit buffer/driver (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE1
56 1OE2
55, 54, 52, 51, 49,
48, 47, 45, 44
2, 3, 5, 6, 8,
9, 10, 12, 13
4, 11, 14, 15, 18, 25,
32, 39, 42, 43, 46, 53
7, 22, 35, 50 V
28 2OE1
29 2OE2
43, 42, 41, 40, 38,
37, 36, 34, 33, 31
16, 17, 19, 20, 21,
23, 24, 26, 27
LOGIC SYMBOL
2
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
27
1A0 to 1A8 Data inputs
1Y0 to 1Y8 Data outputs
GND Ground (0V)
CC
2A0 to 2A8 Data inputs
2Y0 to 2Y8 Data outputs
156
1OE1
1Y
0
1Y
1
1Y
2
1Y
3
1Y
4
1Y
5
1Y
6
1Y
7
1Y
8
2Y
0
2Y
1
2Y
2
2Y
3
2Y
4
2Y
5
2Y
6
2Y
7
2Y
8
2OE1
Output enable input
(active LOW)
Positive supply voltage
Output enable input
(active LOW)
1OE2
1A
0
1A
1
1A
2
1A
3
1A
4
1A
5
1A
6
1A
7
1A
8
2A
0
2A
1
2A
2
2A
3
2A
4
2A
5
2A
6
2A
7
2A
8
2OE2
74ALVCH16825
FUNCTION TABLE
INPUTS
nOE1 nOE2 A
L L L L
L L H H
H X X Z
X H X Z
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “of f” state
LOGIC SYMBOL (IEEE/IEC)
1OE
1
1
56
2
1OE
2OE1
28
29
2OE
2
1A
55
0
1A
54
1
1A
52
2
1A
51
3
1A
49
55
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
30
4
1A
48
5
1A
47
6
1A
45
7
1A
44
8
41
2A
0
40
2A
1
38
2A
2
37
2A
3
36
2A
4
34
2A
5
2A
33
6
31
2A
7
2A
30
8
&
EN1
&
EN2
1, 1 ∇
1, 2 ∇
OUTPUT
Y
2
3
5
6
8
9
10
12
13
16
17
19
20
21
23
24
26
27
SH00141
1Y
0
1Y
1
1Y
2
1Y
3
1Y
4
1Y
5
1Y
6
1Y
7
1Y
8
2Y
0
2Y
1
2Y
2
2Y
3
2Y
4
2Y
5
2Y
6
2Y
7
2Y
8
1998 Jul 27
28 29
SH00142
3