Philips 74alvch16623 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
74ALVCH16623
16-bit transceiver with dual enable;
3-state
Product specification
Supersedes data of 1998 Aug 31
File under Integrated Circuits, IC24
1999 Sep 20
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
FEATURES
• Complies with JEDEC standard
no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTE flow-through
standard pin-out architecture
• All data inputs have bus hold
circuitry
• Output drive capability 50 Ω
transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVCH16623 isa16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOEAB,nOEBA). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling ofnOEABand nOEBA. Each output reinforces its input in
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OE
BA
shouldbetied to VCCthrougha pull-up resistor and OEABshouldbetied to GND
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
=25°C; tr=tf= 2.5 ns.
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
C
I/O
C
I
C
PD
propagation delay nAn,nBnto nBn,nAnCL= 30 pF; VCC= 2.5 V 2.0 ns
= 50 pF; VCC= 3.3 V 1.9 ns
C
L
input/output capacitance 10.0 pF
input capacitance 3.0 pF
power dissipation capacitance per buffer notes1 and 2
outputs enabled 35 pF
outputs disabled 5 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
P
D=CPD
× V
2
× fi+ Σ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
CL= output load capacitance in pF;
fo= output frequency in MHz;
VCC= supply voltage in Volts;
Σ (CL× V
2
× fo) = sum of outputs.
CC
2. The condition is VI= GND to VCC.
1999 Sep 20 2
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74ALVCH16623DGG −40 to +85 °C 48 TSSOP plastic SOT362-1
FUNCTION TABLE
See note 1.
INPUTS INPUTS/OUTPUTS
nOE
AB
nOE
BA
nA
n
nB
n
L L A = B inputs
H H inputs B = A
LHZZ
H L A=B B=A
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
PINNING
PIN SYMBOL DESCRIPTION
1, 24 1OEAB, 2OE
2, 3, 5, 6, 8, 9, 11, 12 1B
to 1B
0
7
AB
output enable input (active HIGH)
data inputs/outputs
4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V)
7, 18, 31, 42 V
13, 14, 16, 17, 19, 20, 22, 23 2B
25, 48 2
26, 27, 29, 30, 32, 33, 35, 36 2A
37, 38, 40, 41, 43, 44, 46, 47 1A
CC
to 2B
0
7
OEBA, 1OE
to 2A
7
0
to 1A
7
0
BA
DC supply voltage
data inputs/outputs
output enable input (active LOW)
data inputs/outputs
data inputs/outputs
1999 Sep 20 3
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
page
1OE
2OE
AB
1B
1B
GND
1B
1B
V
CC
1B
1B
GND
1B
1B
2B
2B
GND
2B
2B
V
CC
2B
2B
GND
2B
2B
AB
1
2
0
3
1
4
5
2
6
3
7
8
4
9
5
10
11
6
12
7
0
1
2
3
4
5
6
7
16623
13
14
15
16
17
18
19
20
21
22
23
24
MNA307
1OE
48
BA
1A
47
0
1OE
1A
46
1
GND
45
1A
44
2
1A
43
3
V
42
CC
1A
41
4
1A
40
5
GND
39
1A
38
6
1A
37
7
2A
36
0
2A
35
1
GND
34
2A
33
2
2A
32
3
V
31
CC
2A
30
4
2A
29
5
GND
28
2A
27
6
26
2A
7
25
2OE
BA
BA
48
1OE
AB
1
1A
0
47
1A
1
46
1A
2
44
1A
3
43
1A
4
41
1A
5
40
1A
6
38
1A
7
37
1B
1B
1B
1B
1B
1B
1B
1B
0
2
1
3
2
5
3
6
4
8
5
9
6
11
7
12
2OE
BA
25
2OE
AB
24
2A
0
36
2B
0
2B
1
2B
2
2B
3
2B
4
2B
5
2B
6
2B
7
MNA308
13
14
16
17
19
20
22
23
2A
1
35
2A
2
33
2A
3
32
2A
4
30
2A
5
29
2A
6
27
2A
7
26
Fig.1 Pin configuration.
1999 Sep 20 4
Fig.2 Logic symbol.
Philips Semiconductors Product specification
16-bit transceiver with dual enable; 3-state 74ALVCH16623
48
handbook, halfpage
1EN1
1
1EN2
47
44
43
41
40
38
1
2
2
346
5
6
8
9
11
1237
Fig.3 IEC logic symbol.
25
2EN1
24
2EN2
1
36
33
32
30
29
27
2
MNA309
13
1435
16
17
19
20
22
2326
handbook, halfpage
data
input
V
CC
to internal circuit
MNA310
Fig.4 Bus hold circuit.
1999 Sep 20 5
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