Philips 74alvch16601 DATASHEETS

INTEGRATED CIRCUITS

74ALVCH16601

18-bit universal bus transceiver (3-State)

Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook

 

1998 Sep 24

Philips Semiconductors Product specification

CPDPower dissipation capacitance per latch

V

GND to V

1

pF

74AL VCH1660118-bit universal bus transceiver (3-State)

FEA TURES

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•Direct interface with TTL levels

•MULTIBYTE

•Low inductance multiple V

and ground bounce

TM

flow-through standard pin-out architecture

and ground pins for minimum noise

CC

•Current drive ± 24 mA at 3.0 V

•All inputs have bus hold circuitry

•Output drive capability 50Ω transmission lines @ 85°C

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

C

I/O

C

I

NOTES:

is used to determine the dynamic power dissipation (PD in W):

1. C

PD

= CPD × V

P

D

f

= input frequency in MHz; CL = output load capacity in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 (C

= 25°C; tr = tf = 2.5 ns

amb

Propagation delay An, Bn to Bn, An

Input/Output capacitance 8.0 pF Input capacitance 4.0 pF

CC

2

× V

L

× fo) = sum of outputs.

CC

p

2

× fi +  (CL × V

PARAMETER CONDITIONS TYPICAL UNIT

p

2

× fo) where:

CC

p

DESCRIPTION

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE (CP

and CPBA) inputs. For A-to-B data flow, the device operates

AB

in the transparent mode when LE A data is latched if CP is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CP active. When OE state. The clocks can be controlled with the clock-enable inputs (CE

/CEAB).

BA

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LE and CPBA.

To ensure the high impedance state during power up or power down, OE resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF

=

I

BA

CC

and OEBA), latch enable (LEAB and LEBA), and clock

AB

is High. When LEAB is Low, the

is held at a High or Low logic level. If LE

AB

is High, the outputs are in the high-impedance

AB

and OE

should be tied to VCC through a pullup

AB

. When OEAB is Low, the outputs are

AB

3.1

ns

2.8

Outputs enabled 21 Outputs disabled 3

p

AB

BA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER

56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16601 DGG SOT364-1

1998 Sep 24 853-2122 20076

2

Philips Semiconductors Product specification

74ALVCH1660118-bit universal bus transceiver (3-State)

PIN CONFIGURATION

1

OE

AB

2

LE

AB

3

A0

4

GND

5

A1

6

A2

7

V

CC

8

A3

9

A4

10

A5

11

GND

12

A6

13

A7

14

A8

15

A9

16

A10

17

A11

18

GND

19

A12

20

A13

21

A14

22

V

CC

23

A15

24

A16

25

GND

26

A17

OE

27

BA

LE

28

BA

56

CE

55

CP

54

B0

53

GND

52

B1

51

B2

50

V

49

B3

48

B4

47

B5 GND

46 45

B6 B7

44 43

B8 B9

42 41

B10 B11

40 39

GND B12

38 37

B13

36

B14

35

V

34

B15

33

B16

32

GND

31

B17

30

CP CE

29

SW00129

CC

PIN DESCRIPTION

AB

BA BA

PIN NUMBER SYMBOL NAME AND FUNCTION

1 OE 2 LE

AB

Output enable A-to-B Latch enable A-to-B

3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19,

A0 to A17 Data inputs/outputs

20, 21, 23, 24,

26

4, 11, 18, 25,

32, 39, 46, 53

7, 22, 35, 50 V

27 OE 28 LE 29 CE 30 CP

GND Ground (0V)

CC

BA

BA BA

Positive supply voltage Output enable B-to-A Latch enable B-to-A Clock enable B-to-A Clock input B-to-A

54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40,

B0 to B17 Data inputs/outputs

38, 37, 36, 34,

33, 31

55 CP 56 CE

AB

Clock input A-to-B Clock enable A-to-B

LOGIC SYMBOL

3 5 6 8

9 10 12 13 14 15 16 17 19 20 21 23 24 26

OE

1

LE

2

CP

55

CE

56

1998 Sep 24

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17

AB

AB AB

B0

54

B1

52

B2

51

B3

49

B4

48

B5

47

B6

45

B7

44

B8

43

B9

42

B10

41

B11

40

B12

38

B13

37

B14

36

B15

34

B16

33

B17

31

OE

AB

BA

LE

BA

CP

BA

CE

BA

SW00130

27 28

30 29

3

Philips Semiconductors Product specification

OUTPUTS

STATUS

74ALVCH1660118-bit universal bus transceiver (3-State)

LOGIC DIAGRAM (one section)

OE

AB

CE

AB

LE

AB

CP

AB

CP

BA

LE

BA

CE

BA

OE

BA

CE C1

A1

CE

C1

CP

1D

CP

1D

B1

18 IDENTICAL CHANNELS

SW00132

FUNCTION TABLE

INPUTS

CE

XX

X H X X X Z Disabled X

X

H L L X X NC Hold

L L

XX = AB for A-to-B direction, BA for B-to-A direction H = HIGH voltage level L = LOW voltage level h = HIGH state must be present one setup time before the LOW-to-HIGH transition of CP l = LOW state must be present one setup time before the LOW-to-HIGH transition of CP X = Don’t care ↑ = LOW-to-HIGH level transition NC = No change Z = High impedance “off” state

OE

XX

L L

LE

XX

H H

L L

CP

XX

X X

↑ ↑

L H

DATA

H

L

h

l

X X

H L

NC Hold

XX

Transparent

Clock + display

1998 Sep 24

4