Philips 74ALVCH16600DGG Datasheet
INTEGRATED CIRCUITS
74ALVCH16600
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug
IC24 Data Handbook
1998 Sep 24
Philips Semiconductors Product specification
CPDPower dissipation capacitance per latch
V
GND to V
1
pF
74AL VCH1660018-bit universal bus transceiver (3-State)
FEA TURES
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 24 mA at 3.0 V
•All inputs have bus hold circuitry
•Output drive capability 50Ω transmission lines @ 85°C
•MULTIBYTE
•Low inductance multiple V
and ground bounce
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
TM
flow-through standard pin-out architecture
and ground pins for minimum noise
CC
= 25°C; tr = tf = 2.5ns
amb
PARAMETER CONDITIONS TYPICAL UNIT
DESCRIPTION
The 74ALVCH16600 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
(CP
AB
in the transparent mode when LE
A data is latched if CP
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CP
active. When OE
state. The High clock can be controlled with the clock-enable inputs
(CE
BA
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LE
and CPBA.
To ensure the high impedance state during power up or power
down, OE
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
and OEBA), latch enable (LEAB and LEBA), and clock
AB
and CPBA) inputs. For A-to-B data flow, the device operates
is High. When LEAB is Low, the
is held at a High or Low logic level. If LE
AB
is High, the outputs are in the high-impedance
AB
AB
. When OEAB is Low, the outputs are
AB
/CEAB).
and OE
BA
should be tied to VCC through a pullup
AB
AB
BA
t
PHL/tPLH
C
I/O
C
I
Propagation delay
An, Bn to Bn, An
Input/Output capacitance 8.0 pF
Input capacitance 4.0 pF
p
p
p
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
=
I
CC
3.1
2.8
Outputs enabled 21
Outputs disabled 3
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in W):
PD
= CPD × V
P
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
× V
(C
L
2
× fi + (CL × V
CC
2
× fo) = sum of outputs.
CC
2
× fo) where:
CC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16600 DGG SOT364-1
ns
p
1998 Sep 24 853-2123 20077
2
Philips Semiconductors Product specification
74ALVCH1660018-bit universal bus transceiver (3-State)
PIN CONFIGURATION
1
OE
AB
2
LE
AB
3
A0
4
GND
5
A1
6
A2
7
V
CC
8
A3
9
A4
10
A5
11
GND
12
A6
13
A7
14
A8
15
A9
16
A10
17
A11
18
GND
19
A12
20
A13
21
A14
22
V
CC
23
A15
24
A16
25
GND
26
A17
OE
27
BA
LE
28
BA
SW00124
PIN DESCRIPTION
56
CE
AB
55
CP
AB
54
B0
53
GND
52
B1
51
B2
50
V
CC
49
B3
48
B4
47
B5
GND
46
45
B6
B7
44
43
B8
B9
42
41
B10
B11
40
39
GND
B12
38
37
B13
36
B14
35
V
CC
34
B15
33
B16
32
GND
31
B17
30
CP
BA
CE
29
BA
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE
2 LE
AB
AB
Output enable A-to-B
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
A0 to A17 Data inputs/outputs
20, 21, 23, 24,
26
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50 V
27 OE
28 LE
29 CE
30 CP
GND Ground (0V)
CC
BA
BA
BA
BA
Positive supply voltage
Output enable B-to-A
Latch enable B-to-A
Clock enable B-to-A
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
B0 to B17 Data inputs/outputs
38, 37, 36, 34,
33, 31
55 CP
56 CE
AB
AB
Clock input A-to-B
Clock enable A-to-B
LOGIC SYMBOL
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
OE
1
LE
2
CP
55
CE
56
1998 Sep 24
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
AB
AB
AB
B0
54
B1
52
B2
51
B3
49
B4
48
B5
47
B6
45
B7
44
B8
43
B9
42
B10
41
B11
40
B12
38
B13
37
B14
36
B15
34
B16
33
B17
31
OE
AB
BA
LE
BA
CP
BA
CE
BA
SW00125
27
28
30
29
3
Philips Semiconductors Product specification
OUTPUTS
STATUS
74ALVCH1660018-bit universal bus transceiver (3-State)
LOGIC DIAGRAM (one section)
OE
AB
CE
AB
LE
AB
CP
AB
CP
BA
LE
BA
CE
BA
OE
BA
CE
C1
A1
CE
C1
CP
1D
CP
1D
B1
18 IDENTICAL CHANNELS
FUNCTION TABLE
INPUTS
CE
XX
X H X X X Z Disabled
X
X
H L L X X NC Hold
L
L
L
L
XX = AB for A-to-B direction, BA for B-to-A direction
H = HIGH voltage level
L = LOW voltage level
h = HIGH state must be present one setup time before the LOW-to-HIGH transition of CP
l = LOW state must be present one setup time before the LOW-to-HIGH transition of CP
X = Don’t care
↓ = HIGH-to-LOW level transition
NC = No change
Z = High impedance “off” state
OE
XX
L
L
L
L
L
L
LE
XX
H
H
L
L
L
L
CP
XX
X
X
↓
↓
H
L
DATA
H
L
h
l
X
X
H
L
H
L
NC Hold
XX
XX
SW00131
Transparent
Clock + display
1998 Sep 24
4
Philips Semiconductors Product specification
74ALVCH1660018-bit universal bus transceiver (3-State)
LOGIC SYMBOL (IEEE/IEC)
OE
CE
OE
CE
CP
CP
LE
LE
A10
A11
A12
A13
A14
A15
A16
A17
1
AB
56
AB
55
AB
2
AB
27
BA
29
BA
30
BA
28
BA
3
A0
5
A1
6
A2
8
A3
9
A4
10
A5
12
A6
13
A7
14
A8
15
A9
16
17
19
20
21
23
24
26
EN1
G2
2C3
C3
G2
EN4
G5
5C6
C6
G5
3D
46D
BUSHOLD CIRCUIT
V
CC
Data Input
54
1
B0
52
B1
51
B2
49
B3
48
B4
47
B5
45
B6
44
B7
43
B8
42
B9
41
B10
40
B11
38
B12
37
B13
36
B14
34
B15
33
B16
31
B17
SW00126
To internal circuit
SW00050
1998 Sep 24
5
Loading...