Philips 74alvch16540 DATASHEETS
INTEGRATED CIRCUITS
74ALVCH16540
2.5V/3.3V 16-bit buffer/line driver,
inverting, 5V input tolerant (3-State)
Product specification
Supersedes data of 1996 Feb 07
IC24 Data Handbook
1997 Aug 11
Philips Semiconductors Product specification
t
1An to 1Yn;
CPDPower dissipation capacitance per buffer
V
GND to V
1
16-bit buffer/line driver, inverting,
5V input tolerant (3-State)
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTE
•Low inductance multiple V
and ground bounce
•Direct interface with TTL levels
•Bus hold on all data inputs eliminates the need for external pull-up
resistors to hold unused inputs
•Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16540 is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74ALVCH16540 is a 16-bit inverting buffer/line driver with
3-State outputs. The 3-State outputs are controlled by the output
enable inputs 1OE
to assume a high impedance OFF-state.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level. This feature eliminates the need for
external pull-up or pull-down resistors. The device can be used as
four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
QUICK REFERENCE DA TA
GND = 0V; T
SYMBOL
PHL/tPLH
C
I
NOTES:
1. C
PD
P
= CPD × V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
TM
flow-through standard pin-out architecture
and ground pins for minimum noise
CC
and 2OEn. A HIGH on nOEn causes the outputs
n
= 25°C; tr = tf ≤ 2.5ns
amb
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
;
2An to 2Yn
CL = 50pF
VCC = 3.3V
CL = 30pF
VCC = 2.5V
Input capacitance 5.0 pF
p
is used to determine the dynamic power dissipation (PD in W):
× V
L
2
× fi + (CL × V
CC
2
× fo) = sum of outputs.
CC
p
2
× fo) where:
CC
p
PIN CONFIGURATION
=
I
CC
74AL VCH16540
1OE
1
1OE
1
1Y0
2
3
1Y1
4
GND
5
1Y2
1Y3
6
V
7
CC
1Y4
8
1Y5
9
GND
10
1Y6
11
1Y7
12
13
2Y0
14
2Y1
GND
15
2Y2
16
2Y3
17
V
18
CC
2Y4
19
2Y5
20
GND
21
2Y6
22
23
2Y7
24
2OE
1
Outputs enabled 26 pF
Outputs disabled 5 pF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SW00108
2
1A0
1A1
GND
1A2
1A3
V
CC
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
V
CC
2A4
2A5
GND
2A6
2A7
2OE
2
1.8 ns
1.8 ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16540 DL ACH16540 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16540 DGG ACH16540 DGG SOT362-1
1997 Aug 1 1 853-2020 18266
2
Philips Semiconductors Product specification
Data outputs
Data inputs
16-bit buffer/line driver, inverting,
5V input tolerant (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 24 nOE
2, 3, 5, 6, 8, 9,
11, 12
13, 14, 16, 17,
19, 20, 22, 23
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
25, 48 nOE
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
LOGIC SYMBOL
47 2
1A0
46 3
1A1
44 5
1A2
43 6
1A3
41 8
1A4
1Y0 to 1Y7
2Y0 to 2Y7
GND Ground (0V)
CC
2A0 to 2A7
1A0 to 1A7
Output enable input
1
(active LOW)
Positive supply voltage
Output enable input
2
(active LOW)
1Y0
1Y1
1Y2
1Y3
1Y4
2A0
2A1
2A2
2A3
2A4
p
p
36 13
35 14
33 16
32 17
30 19
2Y0
2Y1
2Y2
2Y3
2Y4
LOGIC SYMBOL (IEEE/IEC)
1
1OE
1OE
2OE
2OE
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1
48
2
24
1
25
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
&
&
BUS HOLD CIRCUIT
V
CC
74ALVCH16540
EN1
EN2
2
1
1 ∇
2 ∇1
1Y0
3
1Y1
5
1Y2
6
1Y3
8
1Y4
9
1Y5
11
1Y6
12
1Y7
13
2Y0
14
2Y1
16
2Y2
17
2Y3
19
2Y4
20
2Y5
22
2Y6
23
2Y7
SW00110
40 9
1A5
38 11
1A6
37 12
1A7
1
1OE
1
48
1OE
2
1Y5
1Y6
1Y7
29 20
2A5
27 22
2A6
26 23
2A7
24
2OE
1
25
2OE
2
FUNCTION TABLE
INPUTS OUTPUT
nOE
1
L L L H
L L H L
X H X Z
H X X Z
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
nOE
2
nAn nYn
2Y5
2Y6
2Y7
SW00109
Data Input
To internal circuit
SW00044
1997 Aug 1 1
3
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
I
g
16-bit buffer/line driver, inverting,
74ALVCH16540
5V input tolerant (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
DC supply voltage 2.5V range (for max. speed
performance)
V
CC
DC supply voltage 3.3V range (for max. speed
performance)
DC supply voltage (for low-voltage applications) 1.2 3.6
DC Input voltage range For data input pins 0 V
I
DC Input voltage range For control pins 0 5.5
V
O
T
amb
tr, t
ABSOLUTE MAXIMUM RATINGS
DC output voltage range 0 V
Operating free-air temperature range –40 +85 °C
Input rise and fall times
f
VCC = 2.3 to 3.0V
VCC = 3.0 to 3.6V
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
, I
GND
CC
T
stg
P
TOT
DC supply voltage –0.5 to +4.6 V
DC input diode current VI 0 –50 mA
DC input voltage
DC output diode current V
DC output voltage Note 2 –0.5 to VCC +0.5 V
DC output source or sink current VO = 0 to V
DC VCC or GND current 100 mA
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic medium-shrink SO (SSOP)
–plastic mini-pack (TSSOP)
PARAMETER CONDITIONS RA TING UNIT
For control pins and data inputs of ALVC
2
parts
For data inputs of ALVCH parts
VCC or VO 0 50 mA
O
CC
2
For temperature range: –40 to +125 °C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.3 2.7
3.0 3.6
0
0
20
10
–0.5 to +5.5
–0.5 to VCC +0.5
50 mA
850
600
CC
CC
V
V
ns/V
V
mW
1997 Aug 1 1
4
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