Philips 74alvch16501 DATASHEETS
INTEGRATED CIRCUITS
74ALVCH16501
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 29
Philips Semiconductors Product specification
1
C
V
GND to V
1
F
74AL VCH1650118-bit universal bus transceiver (3-State)
FEA TURES
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 24 mA at 3.0 V
•Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
•All inputs have bushold circuitry
•Output drive capability 50Ω transmission lines @ 85°C
•3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
(CP
AB
in the transparent mode when LE
A data is latched if CP
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
active. When OE
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
and CPBA. The output enables are complimentary (OEAB is active
High, and OE
To ensure the high impedance state during power up or power
down, OE
OE
AB
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
and OEBA), latch enable (LEAB and LEBA), and clock
AB
and CPBA) inputs. For A-to-B data flow, the device operates
is held at a High or Low logic level. If LE
AB
is Low, the outputs are in the high-impedance
AB
is active Low).
BA
should be tied to VCC through a pullup resistor and
BA
should be tied to GND through a pulldown resistor; the
is High. When LEAB is Low, the
AB
. When OEAB is High, the outputs are
AB
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
C
I/O
C
I
PD
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; (CL × V
f
o
= 25°C; tr = tf = 2.5ns
amb
Propagation delay
An, Bn to Bn, An
Input/output capacitance 8.0 pF
Input capacitance 4.0 pF
Power dissipation capacitance per
latch
2
× fi + (CL × V
CC
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
=
I
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
CC
CC
2
CC
× fo) = sum of outputs.
Outputs enabled 21
Outputs disabled 3
2.8
3.0
BA
ns
p
, LE
AB
BA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16501 DGG SOT364-1
1998 Sep 29 853–2091 20106
2
Philips Semiconductors Product specification
74ALVCH1650118-bit universal bus transceiver (3-State)
PIN CONFIGURATION
OE
1
AB
LE
2
AB
3
A0
4
GND
5
A1
6
A2
7
V
CC
A3
8
9
A4
10
A5
11
GND
12
A6
13
A7
14
A8
15
A9
16
A10
17
A11
18
GND
19
A12
20
A13
21
A14
22
V
CC
A15
23
A16
24
25
GND
26
A17
27
OE
BA
LE
28
BA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SW00089
GND
CP
A0
GND
B1
B2
V
CC
B3
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
B13
B14
V
CC
B15
B16
GND
B17
CP
GND
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE
AB
2 LE
AB
AB
Output enable A-to-B
Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
A0 to A17 Data inputs/outputs
20, 21, 23, 24,
26
4, 11, 18, 25,
29, 32, 39, 46,
GND Ground (0V)
53, 56
7, 22, 35, 50 V
27 OE
28 LE
30 CP
CC
BA
BA
BA
Positive supply voltage
Output enable B-to-A
Latch enable B-to-A
Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
B0 to B17 Data inputs/outputs
38, 37, 36, 34,
33, 31
55 CP
AB
Clock input A-to-B
LOGIC SYMBOL (IEEE/IEC)
1
OE
AB
56
CP
AB
2
LE
AB
27
OE
BA
30
CP
BA
28
LE
BA
3
A0
BA
A10
A11
A12
A13
A14
A15
A16
A17
5
A1
6
A2
8
A3
9
A4
10
A5
12
A6
13
A7
14
A8
15
A9
16
17
19
20
21
23
24
26
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D 1 1
416D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
SW00088
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
1998 Sep 29
3
Philips Semiconductors Product specification
74ALVCH1650118-bit universal bus transceiver (3-State)
LOGIC SYMBOL
A0
3
A1
5
A2
6
A3
8
A4
9
A5
10
A6
12
A7
13
A8
14
A9
15
A10
16
A11
17
A12
19
A13
20
A14
21
A15
23
A16
24
A17
26
OE
1
AB
LE
2
AB
CP
55
AB
LOGIC DIAGRAM (one section)
OE
AB
CP
BA
LE
BA
CP
AB
LE
AB
OE
BA
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OE
BA
LE
BA
CP
BA
SW00087
BUS HOLD CIRCUIT
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
Data Input
V
CC
To internal circuit
SW00044
1998 Sep 29
C1
A1
18 IDENTICAL CHANNELS
1D
C1
1D
C1
B1
1D
C1
1D
SW00091
4
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