Philips 74alvch16373 DATASHEETS
INTEGRATED CIRCUITS
74ALVCH16373
2.5V/3.3V 16-bit D-type transparent latch
(3-State)
Product specification
Supersedes data of 1998 Jun 29
IC24 Data Handbook
1999 Sep 20
Philips Semiconductors Product specification
gy
t
ns
gy
CPDPower dissipation capacitance per latch
V
GND to V
1
pF
74AL VCH1637316-bit D-type transparent latch (3-State)
FEA TURES
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTE
•Low inductance multiple V
and ground bounce
TM
flow-through standard pin-out architecture
and ground pins for minimum noise
CC
•Direct interface with TTL levels
•All data inputs have bus hold
•Output drive capability 50Ω transmission lines @ 85°C
•Current drive ±24 mA at 3.0 V
DESCRIPTION
The 74ALVCH16373 is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. Incorporates bus hold data inputs which
eliminate the need for external pull-up or pull-down resistors to hold
unused inputs. One latch enable (LE) input and one output enable
(OE
) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE
available at the outputs. When OE
high impedance OFF-state. Operation of the OE
affect the state of the latches.
is LOW, the contents of the eight latches are
is HIGH, the outputs go to the
input does not
PIN CONFIGURATION
1
1OE
1Q0
2
1Q1
3
GND
4
1Q2
5
1Q3
6
V
7
CC
1Q4
8
1Q5
9
GND
10
1Q6
11
12
1Q7
13
2Q0
2Q1
14
GND
15
2Q2
16
2Q3
17
V
18
CC
2Q4
19
2Q5
20
21
GND
22
2Q6
23
2Q7
24
2OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SW00066
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
CC
2D4
2D5
GND
2D6
2D7
2LE
QUICK REFERENCE DA TA
GND = 0V; T
SYMBOL
PHL/tPLH
C
I
NOTE:
is used to determine the dynamic power dissipation (PD in µW):
1. C
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; S (CL × V
f
o
= 25°C; tr = tf ≤ 2.5ns
amb
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Input capacitance 5.0 pF
2
CC
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C 74ALVCH16373 DL ACH16373 DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16373 DGG ACH16373 DGG SOT362-1
1999 Sep 20 853-2086 22418
PARAMETER CONDITIONS TYPICAL UNIT
p
× fi + S (CL × V
VCC = 2.5V, CL = 30pF 2.1
VCC = 3.3V, CL = 50pF 2.1
VCC = 2.5V, CL = 30pF 2.2
VCC = 3.3V, CL = 50pF 2.2
p
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
CC
p
=
I
CC
CC
2
× fo) = sum of outputs.
Outputs enabled 16
Outputs disabled 10
2
p
Philips Semiconductors Product specification
OPERATING MODES
16-bit D-type transparent latch (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE
2, 3, 5, 6, 8, 9,
11, 12
1Q0 to 1Q7 Data inputs/outputs
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42 V
13, 14, 16, 17,
19, 20, 22, 23
2Q0 to 2Q7 Data inputs/outputs
24 2OE
25 2LE
36, 35, 33, 32,
30, 29, 27, 26
47, 46, 44, 43,
41, 40, 38, 37
2D0 to 2D7 Data inputs
1D0 to 1D7 Data inputs
48 1LE
GND Ground (0V)
CC
Output enable input
(active LOW)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input (active
HIGH)
Latch enable input (active
HIGH)
LOGIC SYMBOL
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
74ALVCH16373
241
1OE 2OE
1LE 2LE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
LOGIC DIAGRAM
1D0
1LE
1OE
DQ
LATCH
1
LE
LE
TO 7 OTHER CHANNELS
1Q0
2D0
2LE
2OE
FUNCTION TABLE (per section of eight bits)
INPUTS
nOE nLE nDn
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs H
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
L
L
L
L
H
H
L
L
L
H
L
48 25
DQ
LATCH
9
LE
LE
TO 7 OTHER CHANNELS
INTERNAL
LATCHES
L
H
l
h
l
h
SW00067
2Q0
SW00068
OUTPUTS
nQn
L
H
L
H
L
H
L
H
L
H
Z
Z
1999 Sep 20
3
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
V
DC Input voltage range
V
16-bit D-type transparent latch (3-State)
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
2OE
2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
1 ∇
2 ∇4D
2
1Q0
3
1Q1
5
1Q2
6
1Q3
8
1Q4
9
1Q5
11
1Q6
12
1Q7
13
2Q0
14
2Q1
16
2Q2
17
2Q3
19
2Q4
20
2Q5
22
2Q6
23
2Q7
SW00524
BUS HOLD CIRCUIT
V
CC
Data Input
74ALVCH16373
To internal circuit
SW00044
RECOMMENDED OPERATING CONDITIONS
DC supply voltage 2.5V range (for max. speed
CC
V
O
T
amb
tr, t
performance @ 30 pF output load)
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
I
p
DC output voltage range 0 V
Operating free-air temperature range –40 +85 °C
Input rise and fall times
f
LIMITS
MIN MAX
2.3 2.7
3.0 3.6
For data input pins 0 V
For control pins 0 5.5
VCC = 2.3 to 3.0V
VCC = 3.0 to 3.6V
0
0
20
10
CC
CC
V
ns/V
1999 Sep 20
4
Loading...