Philips 74alvch162827 DATASHEETS
INTEGRATED CIRCUITS
74ALVCH162827
20-bit buffer/line driver, non-inverting,
with 30 termination resistors (3-State)
Product specification
IC24 Data Handbook
1998 Sep 29
Philips Semiconductors Product specification
1
CPDPower dissi ation ca acitance er latch
V
GND to V
1
F
20-bit buffer/line driver, non-inverting, with 30Ω
termination resistors (3-State)
FEA TURES
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 12 mA at 3.0 V
•MULTIBYTE
•Low inductance multiple V
and ground bounce
TM
flow-through standard pin-out architecture
and GND pins for minimum noise
CC
•Integrated 30 W termination resistors
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
C
I
NOTES:
1. C
PD
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
S (C
= 25°C; tr = tf = 2.5ns
amb
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
nAn to nYn
Input capacitance 5 pF
p
is used to determine the dynamic power dissipation (PD in mW):
= CPD × V
× V
L
2
× fi + S (CL × V
CC
2
× fo) = sum of outputs.
CC
p
2
× fo) where:
CC
p
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
DESCRIPTION
The 74ALVCH162827 high-performance CMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ALVCH162827 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NAND Output Enables (nOE
maximum control flexibility.
The 74ALVCH162827 is designed with 30Ω series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers
and bus receivers/transmitters.
To ensure the high impedance state during power up or power
down, OE
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
=
I
CC
74ALVCH162827
1, nOE2) for
should be tied to VCC through a pullup resistor; the
2.9
2.9
Output enabled 14
Output disabled 3
ns
p
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH162827DGG ACH162827DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
1998 Sep 29 853-2127 20100
1, 56,
28, 29
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
1OE1 1OE2,
2OE1, 2OE2
CC
Data inputs
Data outputs
Output enable inputs (active-LOW)
Positive supply voltage
2
Philips Semiconductors Product specification
OPERATING MODE
20-bit buffer/line driver, non-inverting, with 30Ω
termination resistors (3-State)
PIN CONFIGURATION
1
2
1Y0
3
1Y1
4
GND
5
1Y2
6
1Y3
7
V
CC
8
1Y4
9
1Y5
10
1Y6
GND
11
1Y7
12
1Y8
13
1Y9
14
2Y0
15
2Y1
16
2Y2
17
GND
18
2Y3
19
2Y4
20
2Y5
21
V
22
CC
23
2Y6
24
2Y7
25
GND
26
2Y8
27
2Y9
28 29
2OE
1
561OE1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
SH00010
1OE
1A0
1A1
GND
1A2
1A3
V
CC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A0
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OE
2
2
LOGIC SYMBOL (IEEE/IEC)
1OE1
1OE
2OE
2OE
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
74ALVCH162827
1
56
2
28
1
29
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
&
EN1
&
EN2
2
1 ∇
1
2 ∇
1
SH00012
1Y0
3
1Y1
5
1Y2
6
1Y3
8
1Y4
9
1Y5
10
1Y6
12
1Y7
13
1Y8
14
1Y9
15
2Y0
16
2Y1
17
2Y2
19
2Y3
20
2Y4
21
2Y5
23
2Y6
24
2Y7
26
2Y8
27
2Y9
LOGIC SYMBOL
1
56
28
29
1998 Sep 29
55 54 52 51 49 48 47 45 44 43
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1OE1
1OE2
1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2OE1
2OE2
2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7
15 16 17 19 20 21 23 24 26 27
1A8 1A9
1Y8 1Y9
2A8 2A9
2Y8 2Y9
FUNCTION TABLE
INPUTS OUTPUT
nOE1 nOE2 nAn nYn
L L L L Transparent
L L H H Transparent
H X X Z High impedance
X H X Z High impedance
X = Don’t care
Z = High impedance “off” state
H = High voltage level
L = Low voltage level
SH00011
3
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