Philips 74ALVCH162601DGG Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74ALVCH162601
18-bituniversalbustransceiverwith
30 Ω termination resistor; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Oct 14
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
FEATURES
• Complies with JEDEC standard
no. 8-1A
• CMOS low power consumption
• Direct interface with TTL levels
• MULTIBYTE flow-through
standard pin-out architecture
• Low inductance multiple VCC and
ground pinsfor minimum noise and
ground bounce
• All data inputs have bus hold
circuitry
• Integrated 30 Ω termination
resistors.
DESCRIPTION
The 74ALVCH162601is an 18-bituniversal transceiver featuringnon-inverting
3-state bus compatible outputs in both send and receive directions. Data flow
in each direction is controlled by output enable (OEAB and OEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched ifCPABis heldat a HIGH or LOWlogic level. IfLEABis LOW,the A-bus
data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs
are in the high-impedance state. The clocks can be controlled with the
clock-enable inputs (CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,LEBAand CPBA.
To ensure the high-impedance state during power-down, OEBA and OE
should be tied to VCC through a pull-up resistor, the minimum value of the
resistor is determined by the current-sinking/current-sourcing capability of the
driver.
The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or
LOW output stage.
74ALVCH162601
AB
Active bus hold circuitry is provided to hold unused or floating data inputs at
a valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
=25°C; tr=tf= 2.5 ns.
amb
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
C
I/O
C
I
C
PD
propagation delay An,Bnto Bn,AnCL= 30 pF; VCC= 2.5 V 4.0 ns
C
= 50 pF; VCC= 3.3 V 3.1 ns
L
input/output capacitance 8.0 pF
input capacitance 4.0 pF
power dissipation capacitance per
latch
notes 1 and 2
outputs enabled 21 pF
outputs disabled 3 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
P
D=CPD
× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
1999 Oct 14 2
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
74ALVCH162601
termination resistor; 3-state
FUNCTION TABLE
See note 1.
INPUTS
CE
XX
X H X X X Z disabled
X
X
H L L X X NC hold
L
L
L
L
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level;
L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of CPXX;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of CPXX;
X = don’t care;
↑ = LOW-to-HIGH level transition;
NC = no change;
Z = high-impedance OFF-state.
OE
XX
L
L
L
L
L
L
LE
XX
H
H
L
L
L
L
CP
XX
X
X
↑
↑
L
H
An,B
H
L
h
l
X
X
n
OUTPUTS STATUS
H
L
H
L
NC hold
transparent
clock and display
ORDERING INFORMATION
TYPE NUMBER
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74ALVCH162601DGG −40 to +85 °C 56 TSSOP plastic SOT364-1
1999 Oct 14 3
PACKAGE
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
PINNING
PIN SYMBOL DESCRIPTION
1
2LE
3, 5,6, 8, 9, 10, 12, 13, 14,15,
OE
A
0
AB
AB
to A
17
16, 17, 19, 20, 21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46, 53 GND ground (0 V)
7, 22, 35, 50 V
27
28 LE
29
30 CP
31, 33, 34, 36, 37, 38, 40, 41,
OE
CE
B
CC
17
BA
BA
BA
BA
to B
0
42, 43, 44, 45, 47, 48, 49, 51,
52, 54
55 CP
56
CE
AB
AB
output enable A-to-B
latch enable A-to-B
data inputs/outputs
DC supply voltage
output enable B-to-A
latch enable B-to-A
clock enable B-to-A
clock input B-to-A
data inputs/outputs
clock input A-to-B
clock enable A-to-B
74ALVCH162601
1999 Oct 14 4
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
handbook, halfpage
OE
LE
OE
LE
AB
AB
A
GND
A
A
V
CC
A
A
A
GND
A
A
A
A
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
BA
BA
1
2
3
0
4
5
1
6
2
7
8
3
9
4
10
5
11
12
6
13
7
14
8
9
162601
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MNA287
CE
56
AB
CP
55
AB
B
54
0
GND
53
B
52
1
B
51
2
V
50
CC
B
49
3
B
48
4
B
47
5
GND
46
B
45
6
B
44
7
B
43
8
B
42
9
B
41
10
B
40
11
GND
39
B
38
12
B
37
13
B
36
14
V
35
CC
B
34
15
B
33
16
GND
32
B
31
17
CP
30
BA
CE
29
BA
handbook, halfpage
data
input
74ALVCH162601
V
CC
MNA291
Fig.2 Bus hold circuit.
to internal circuit
Fig.1 Pin configuration.
1999 Oct 14 5
Philips Semiconductors Product specification
18-bit universal bus transceiver with 30 Ω
termination resistor; 3-state
handbook, full pagewidth
OE
CE
LE
CP
CP
LE
CE
OE
AB
AB
AB
AB
BA
BA
BA
BA
A
n
CE
C1
1D
CP
74ALVCH162601
B
n
CE
C1
CP
1D
18 IDENTICAL CHANNELS
Fig.3 Logic diagram (one section).
MNA289
1999 Oct 14 6
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