Philips 74alvc16835a DATASHEETS

INTEGRATED CIRCUITS

74ALVC16835A

18-bit registered driver (3-State)

Product specification Replaces datasheet 74ALVC16835 of 1999 Mar 18 IC24 Data Handbook

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2000 Mar 14

Philips Semiconductors Product specification

CPDPower dissipation capacitance per buffer

V

GND to V

1

pF

18-bit registered driver (3-State)

FEA TURES

•Wide supply voltage range of 1.2 V to 3.6 V

•Complies with JEDEC standard no. 8-1A.

•CMOS low power consumption

•Direct interface with TTL levels

•Current drive ± 24 mA at 3.0 V

•MULTIBYTE

•Low inductance multiple V

and ground bounce

•Output drive capability 50 Ω transmission lines @ 85°C

•Input diodes to accommodate strong drivers

DESCRIPTION

The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE (LE

) and clock inputs (CP).

When LE HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

When OE outputs go to the high impedance OFF–state. Operation of the OE input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE minimum value of the resistor is determined by the current-sinking capability of the driver.

TM

flow-through standard pin-out architecture

and GND pins for minimum noise

CC

), active low latch enable

is LOW, the A to Y data flow is transparent. When LE is

is LOW the outputs are active. When OE is HIGH, the

should be tied to VCC through a pullup resistor; the

PIN CONFIGURATION

1 2

NC

3

Y

1

4

GND

5

Y

2

6

Y

3

7

V

CC

8

Y

4

9

Y

5

Y

10

6

GND

11

Y

12

7

Y

13

8

14

Y

9

15

Y

10

16

Y

11

17

Y

12

18

GND

19

Y

13

20

Y

14

21

Y

15

22

V

CC

23

Y

16

24

Y

17

25

GND

26

Y

18

27

OE

28 29

LE

74AL VC16835A

GND

56NC

NC

55

A

54

1

53

GND

52

A

2

51

A

3

50

V

CC

49

A

4

48

A

5

A

47

6

GND

46

A

45

7

A

44

8

43

A

9

42

A

10

41

A

11

40

A

12

39

GND

38

A

13

37

A

14

36

A

15

35

V

CC

34

A

16

33

A

17

32

GND

31

A

18

30

CP GND

QUICK REFERENCE DA TA

GND = 0 V; T

SYMBOL

t

PHL/tPLH

f

max

C

I

C

I/O

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

= CPD × V

P

D

= output frequency in MHz; VCC = supply voltage in V; S (CL × V

f

o

2000 Mar 14 853–2190 23314

= 25°C; tr = tf ≤ 2.5 ns

amb

Propagation delay An to Yn; LE to Yn; CP to Yn

Maximum clock frequency VCC = 3.3 V, CL = 50 pF 350 MHz Input capacitance 4.0 pF Input/Output capacitance 8.0 pF

2

× fi + S (CL × V

CC

SH00188

PARAMETER CONDITIONS TYPICAL UNIT

VCC = 3.3 V, CL = 50 pF

2.3

2.6

2.5

transparent mode

Output enabled

p

=

I

CC

Output disabled

Clocked mode Output enabled Output disabled

2

× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

CC

2

× fo) = sum of outputs.

CC

13

3

22 15

2

ns

p

Philips Semiconductors Product specification

18-bit registered driver (3-State)

74ALVC16835A

ORDERING INFORMATION

PACKAGES

TEMPERATURE

RANGE

ORDER CODE

56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVC16835A DGG SOT364-1

PIN DESCRIPTION

LOGIC SYMBOL

PIN NUMBER SYMBOL NAME AND FUNCTION

1, 2, 55 NC No connection

OE

3, 5, 6, 8, 9, 10, 12, 13,

14, 15, 16, 17, 19, 20,

Y1 to Y18Data outputs

21, 23, 24, 26

4, 11, 18, 25, 32, 39, 46,

53, 56

7, 22, 35, 50 V

27 OE

28 LE

GND Ground (0V)

Positive supply voltage

CC

Output enable input (active LOW)

Latch enable input (active LOW)

CP

LE

30 CP Clock input

54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40,

38, 37, 36, 34, 33, 31

A1 to A18Data inputs

A

1

D

LE

CP

DRAWING

NUMBER

Y

1

TO THE 17 OTHER CHANNELS

TYPICAL INPUT (DATA OR CONTROL)

V

CC

A1

SH00200

SH00203

2000 Mar 14

3

Philips Semiconductors Product specification

OUTPUTS

18-bit registered driver (3-State)

LOGIC SYMBOL (IEEE/IEC)

27

OE

30

CP

28

LE

3

Y

1

5

Y

2

6

Y

3

8

Y

4

9

Y

5

10

Y

6

12

Y

7

13

Y

8

14

Y

9

15

Y

10

16

Y

11

17

Y

12

19

Y

13

20

Y

14

21

Y

15

23

Y

16

24

Y

17

Y

25

18

EN5

G7

4D

8D

3C4

1, 2 ∇

5, 6 ∇

54 52 51 49 48 47 45 44 43 42

41 40 38 37 36 34 33 31

SH00190

74ALVC16835A

FUNCTION TABLE

INPUTS

OE LE CP A

H X X X Z L H X L L L H X H H

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10

A

11

A

12

A

13

A

14

A

15

A

16

A

17

A

18

L L ↑ L L L L ↑ H H L L H X Y L L L X Y

1

0

2

0

H = HIGH voltage level L = LOW voltage level X = Don’t care Z = High impedance “off” state ↑ = LOW-to-HIGH level transition

NOTES:

1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low.

2. Output level before the indicated steady-state input conditions were established.

2000 Mar 14

4