Philips 74ALVC162836A Datasheet
INTEGRATED CIRCUITS
74ALVC162836A
20-bit registered driver with inverted
register enable and 30Ω termination
resistors (3-State)
Product specification
Replaces datasheet 74ALVC162836 of 2000 Jan 03
IC24 Data Handbook
2000 Mar 14
Philips Semiconductors Product specification
CPDPower dissipation capacitance per buffer
V
GND to V
1
pF
20-bit registered driver with inverted register enable
and 30Ω termination resistors (3-State)
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 12 mA at 3.0 V
•MULTIBYTE
•Low inductance multiple V
and ground bounce
TM
flow-through standard pin-out architecture
and GND pins for minimum noise
CC
•Output drive capability 50 Ω transmission lines @ 85°C
•Integrated 30 W termination resistors
•Diode clamps to V
and GND on all inputs
CC
•Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162836A is an 20-bit universal bus driver. Data flow is
controlled by output enable (OE
(CP).
When LE
is HIGH, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162836A is designed with 30 W_series resistors in both
HIGH or LOW output stages.
When OE
is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE
should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
), latch enable (LE) and clock inputs
PIN CONFIGURATION
1
2
Y
1
3
Y
2
4
GND
5
Y
3
6
Y
4
7
V
CC
8
Y
5
Y
9
6
10
Y
7
GND
11
12
Y
8
Y
13
9
14
Y
10
15
Y
11
16
Y
12
17
Y
13
18
GND
19
Y
14
20
Y
15
21
Y
16
22
V
CC
23
Y
17
24
Y
18
25
GND
26
Y
19
Y
27
20
28 29
NC
74AL VC162836A
56OE
CP
55
A
1
54
A
2
53
GND
52
A
3
51
A
4
50
V
CC
49
A
5
48
A
6
47
A
7
GND
46
45
A
8
A
44
9
43
A
10
42
A
11
41
A
12
40
A
13
39
GND
38
A
14
37
A
15
36
A
16
35
V
CC
A
34
17
33
A
18
32
GND
31
A
19
30
A
20
LE
SH00197
QUICK REFERENCE DA TA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
I/O
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; S (CL × V
f
o
2000 Mar 14 853–2195 23314
= 25°C; tr = tf ≤ 2.5ns
amb
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
Maximum clock frequency VCC = 3.3 V, CL = 50 pF 240 MHz
Input capacitance 4.0 pF
Input/Output capacitance 8.0 pF
2
× fi + S (CL × V
CC
PARAMETER CONDITIONS TYPICAL UNIT
VCC = 3.3 V, CL = 50 pF
2.9
3.5
3.3
transparent mode
Output enabled
p
p
p
=
I
CC
Output disabled
Clocked mode
Output enabled
Output disabled
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
CC
2
× fo) = sum of outputs.
CC
10
3
21
15
2
ns
p
Philips Semiconductors Product specification
20-bit registered driver with inverted register enable
74ALVC162836A
and 30Ω termination resistors (3-State)
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
ORDER CODE
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVC162836A DGG SOT364-1
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER SYMBOL NAME AND FUNCTION
28 NC No connection
2, 3, 5, 6, 8, 9, 10, 12,
13, 14, 15, 16, 17, 19,
Y1 to Y18Data outputs
OE
20, 21, 23, 24, 26, 27
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50 V
1 OE
29 LE
GND Ground (0V)
CC
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
CP
LE
56 CP Clock input
55, 54, 52, 51, 49, 48,
47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33,
31, 30
A1 to A18Data inputs
A
1
D
LE
CP
DRAWING
NUMBER
Y
1
TO THE 17 OTHER CHANNELS
TYPICAL INPUT (DATA OR CONTROL)
V
CC
A1
SH00200
SH00202
2000 Mar 14
3
Philips Semiconductors Product specification
20-bit registered driver with inverted register enable
and 30Ω termination resistors (3-State)
LOGIC SYMBOL (IEEE/IEC)
27
OE
30
CP
28
LE
3
Y
0
5
Y
1
6
Y
2
8
Y
3
9
Y
4
10
Y
5
12
Y
6
13
Y
7
14
Y
8
15
Y
9
16
Y
10
17
Y
11
19
Y
12
20
Y
13
21
Y
14
23
Y
15
24
Y
16
25
Y
17
EN5
3C4
G7
4D
8D
1, 2 ∇
5, 6 ∇
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
SH00193
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
FUNCTION TABLE
OE LE CP A
H X X X Z
L L X L L
L L X H H
L H ↑ L L
L H ↑ H H
L H H X Y
L H L X Y
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
↑ = LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE
2. Output level before the indicated steady-state input conditions
were established.
INPUTS
74ALVC162836A
OUTPUTS
Y
1
0
2
0
goes low.
2000 Mar 14
4
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