Philips 74ALVC16244DL, 74ALVC16244DGG, 74ALVCH16244DL, 74ALVCH16244DGG Datasheet

INTEGRATED CIRCUITS

74ALVC16244/74ALVCH16244

2.5V/3.3V 16-bit buffer/line driver (3-State)

Product specification

1998 Jun 29

Supersedes data of 1997 Mar 21

IC24 Data Handbook

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	Philips Semiconductors	Product specification
	16-bit buffer/line driver (3-State)	74ALVC16244/
		74ALVCH16244

FEATURES

•Wide supply voltage range of 1.2V to 3.6V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•MULTIBYTETM flow-through standard pin-out architecture

•Low inductance multiple VCC and GND pins for minimum noise and ground bounce

•Direct interface with TTL levels

•Bus hold on data inputs (74ALVCH16244 only)

•Output drive capability 50W transmission lines @ 85°C

•Current drive ±24 mA at 3.0 V

DESCRIPTION

The 74ALVC16244(74ALVCH16244) is a 16-bit non-inverting buffer/line driver with 3-State outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A

HIGH on nOE causes the outputs to assume a high impedance OFF-state.

The 74ALVCH16244 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

The 74ALVC16244 has 5V tolerant inputs.

PIN CONFIGURATION

			1				48	2OE
1OE
1Y0			2				47	1A0
1Y1			3				46	1A1
GND			4				45	GND
1Y2			5				44	1A2
1Y3			6				43	1A3
VCC			7				42	VCC
2Y0			8				41	2A0
2Y1			9				40	2A1
GND			10				39	GND
2Y2			11				38	2A2
2Y3			12				37	2A3
3Y0			13				36	3A0
3Y1			14				35	3A1
GND			15				34	GND
3Y2			16				33	3A2
3Y3			17				32	3A3
VCC			18				31	VCC
4Y0			19				30	4A0
4Y1			20				29	4A1
GND			21				28	GND
4Y2			22				27	4A2
4Y3			23				26	4A3
			24				25	3OE
4OE
						SW00194

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL	PARAMETER	CONDITIONS		TYPICAL	UNIT
tPHL/tPLH	Propagation delay	VCC = 2.5V, CL = 30pF		1.9	ns
	An to Yn	VCC = 3.3V, CL = 50pF		1.9
CI	Input capacitance			5.0	pF
		1	Outputs enabled	25
CPD	Power dissipation capacitance per buffer	VI = GND to VCC	Outputs disabled	4	pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
48-Pin Plastic SSOP Type III	±40°C to +85°C	74ALVC16244 DL	AC16244 DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74ALVC16244 DGG	AC16244 DGG	SOT362-1
48-Pin Plastic SSOP Type III	±40°C to +85°C	74ALVCH16244 DL	ACH16244 DL	SOT370-1
48-Pin Plastic TSSOP Type II	±40°C to +85°C	74ALVCH16244 DGG	ACH16244 DGG	SOT362-1

1998 Jun 29

2

853-2082 19638

Philips Semiconductors	Product specification

16-bit buffer/line driver (3-State)

74ALVC16244/

74ALVCH16244

PIN DESCRIPTION

	PIN NUMBER	SYMBOL			NAME AND FUNCTION
					Output enable input
	1	1OE
					(active LOW)
	2, 3, 5, 6	1Y0 to 1Y3			Data outputs
	4, 10, 15, 21,	GND			Ground (0V)
	28, 34, 39, 45
	7, 18, 31, 42	VCC			Positive supply voltage
	8, 9, 11, 12	2Y0 to 2Y3			Data outputs
	13, 14, 16, 17	3Y0 to 3Y3			Data outputs
	19, 20, 22, 23	4Y0 to 4Y3			Data outputs
					Output enable input
	24	4OE
					(active LOW)
					Output enable input
	25	3OE
					(active LOW)
	30, 29, 27, 26	4A0 to 4A3			Data inputs
	36, 35, 33, 32	3A0 to 3A3			Data inputs
	41, 40, 38, 37	2A0 to 2A3			Data inputs
	47, 46, 44, 43	1A0 to 1A3			Data inputs
					Output enable input
	48	2OE
					(active LOW)

LOGIC SYMBOL

47	2	1Y0	36	13
1A0			3A0	3Y0
46	3	1Y1	35	14
1A1			3A1	3Y1
44	5	1Y2	33	16
1A2			3A2	3Y2
43	6	1Y3	32	17
1A3			3A3	3Y3
1			25
1OE			3OE
41	8	2Y0	30	19
2A0			4A0	4Y0
40	9	2Y1	29	20
2A1			4A1	4Y1
38	11	2Y2	27	22
2A2			4A2	4Y2
37	12	2Y3	26	23
2A3			4A3	4Y3
48			24
2OE			4OE

FUNCTION TABLE

							INPUTS							OUTPUT
											nAn				nYn
nOE
		L									L				L
		L									H				H
		H									X				Z
H = HIGH voltage level
L = LOW voltage level
X = don't care
Z = high impedance OFF-state
LOGIC SYMBOL (IEEE/IEC)
							1
										1EN
1OE
							48
										2EN
2OE
							25
										3EN
3OE
							24			4EN
4OE
							47							2
1A0										1		1			1Y0
							46							3
1A1															1Y1
							44							5
1A2															1Y2
							43							6
1A3															1Y3
							41							8
2A0															2Y0
										1		2
							40							9
2A1															2Y1
							38							11
2A2															2Y2
							37							12
2A3															2Y3
							36							13
3A0															3Y0
										1		3
							35							14
3A1															3Y1
3A2							33							16	3Y2
							32							17
3A3															3Y3
							30							19
4A0															4Y0
										1		4
							29							20
4A1															4Y1
							27							22
4A2															4Y2
							26							23
4A3															4Y3
														SW00056

BUS HOLD CIRCUIT

VCC

Data Input

To internal circuit

SW00195

SW00044

1998 Jun 29

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