Philips 74ALVC162334A Datasheet
INTEGRATED CIRCUITS
74ALVC162334A
16-bit registered driver with inverted
register enable and 30Ω termination
resistors (3-State)
Product specification
Replaces datasheet 74ALVC162334 of 1999 Oct 24
IC24 Data Handbook
2000 Mar 14
Philips Semiconductors Product specification
CPDPower dissipation capacitance per buffer
V
GND to V
1
pF
16-bit registered driver with inverted register enable
and 30Ω termination resistors (3-State)
FEA TURES
•Wide supply voltage range of 1.2 V to 3.6 V
•Complies with JEDEC standard no. 8-1A.
•CMOS low power consumption
•Direct interface with TTL levels
•Current drive ± 24 mA at 3.0 V
•MULTIBYTE
•Low inductance multiple V
and ground bounce
TM
flow-through standard pin-out architecture
and GND pins for minimum noise
CC
•Output drive capability 50 Ω transmission lines @ 85°C
•Current drive ±24 mA at 3.0 V
•Integrated 30 Ω termination resistors
•Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162334A is an 16-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162334A is designed with 30 Ω series resistors in both
HIGH or LOW output stages.
When OE
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE
minimum value of the resistor is determined by the current-sinking
capability of the driver.
is LOW, the A to Y data flow is transparent. When LE is
is LOW the outputs are active. When OE is HIGH, the
should be tied to VCC through a pullup resistor; the
PIN CONFIGURATION
1
2
Y
1
3
Y
2
4
GND
5
Y
3
6
Y
4
7
V
CC
8
Y
5
9
Y
6
10
GND
11
Y
7
12
Y
8
13
Y
9
14
Y
10
15
GND
16
Y
11
17
Y
12
18
V
CC
19
Y
13
20
Y
14
21
GND
Y
22
15
23
Y
16
24 25
NC
74AL VC162334A
CP
48OE
47
A
1
46
A
2
GND
45
44
A
3
43
A
4
42
V
CC
41
A
5
40
A
6
39
GND
38
A
7
37
A
8
36
A
9
35
A
10
34
GND
33
A
11
32
A
12
31
V
CC
30
A
13
29
A
14
28
GND
27
A
15
26
A
16
LE
SH00198
QUICK REFERENCE DA TA
GND = 0 V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
I/O
NOTES:
is used to determine the dynamic power dissipation (PD in µW):
1. C
PD
= CPD × V
P
D
= output frequency in MHz; VCC = supply voltage in V; S (CL × V
f
o
2000 Mar 14 853-2197 23314
= 25°C; tr = tf ≤ 2.5 ns
amb
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
Maximum clock frequency VCC = 3.3 V, CL = 50 pF 240 MHz
Input capacitance 4.0 pF
Input/Output capacitance 8.0 pF
2
× fi + S (CL × V
CC
PARAMETER CONDITIONS TYPICAL UNIT
VCC = 3.3 V, CL = 50 pF
2.9
3.5
3.3
transparent mode
Output enabled
p
p
p
=
I
CC
Output disabled
Clocked mode
Output enabled
Output disabled
2
× fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
CC
2
× fo) = sum of outputs.
CC
10
3
21
15
2
ns
p
Philips Semiconductors Product specification
16-bit registered driver with inverted register enable
74ALVC162334A
and 30Ω termination resistors (3-State)
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
ORDER CODE
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVC162334A DGG SOT364-1
PIN DESCRIPTION
LOGIC SYMBOL
PIN NUMBER SYMBOL NAME AND FUNCTION
24 NC No connection
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
Y1 to Y18Data outputs
10, 15, 21, 28, 34, 45 GND Ground (0V)
7, 22, 35, 50 V
1 OE
25 LE
CC
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
OE
CP
LE
A
0
D
LE
CP
48 CP Clock input
26, 27, 29, 30, 32, 37,
38, 40, 41, 43, 44, 46, 47
A1 to A18Data inputs
TO THE 17 OTHER CHANNELS
DRAWING
NUMBER
Y
0
SH00157
LOGIC SYMBOL (IEEE/IEC)
1
OE
48
CP
25
LE
2
Y
1
3
Y
2
5
Y
3
6
Y
4
8
Y
5
9
Y
6
11
Y
7
12
Y
8
13
Y
9
14
Y
10
16
Y
11
17
Y
12
19
Y
13
20
Y
14
21
Y
15
23
Y
16
EN1
2C3
C3
G2
1 ∇ 1
TYPICAL INPUT (DATA OR CONTROL)
V
CC
A1
47
A
1
46
A
2
44
A
3
3D
43
41
40
38
37
36
35
33
32
30
29
27
26
SH00199
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
FUNCTION TABLE
INPUTS
OE LE CP A
H X X X Z
L L X L L
L L X H H
L H ↑ L L
L H ↑ H H
L H H X Y
L H L X Y
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
↑ = LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE
2. Output level before the indicated steady-state input conditions
were established.
SH00200
OUTPUTS
Y
1
0
2
0
goes low.
2000 Mar 14
3
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