Philips 74als646 1 648 DATASHEETS
INTEGRATED CIRCUITS
74ALS646/74ALS646–1
74ALS648/74ALS648–1
Transceiver/register
Product specification
IC05 Data Handbook
1991 Feb 08
Philips Semiconductors Product specification
T ransceiver/register
74ALS646/646-1 Octal transceiver/register, non-inverting (3-State)
74ALS648/648-1 Octal transceiver/register, inverting (3-State)
FEA TURES
•Combines 74ALS245 and two 74ALS374 type functions in
one chip
•Independent registers for A and B buses
•Multiplexed real-time and stored data
•Choice of non-inverting and inverting data paths
•3-State outputs
•The -1 version sink 48mA I
DESCRIPTION
The 74ALS646/74ALS646-1 and 74ALS648/74ALS648-1
transceivers/registers consist of bus transceiver circuits with 3-State
outputs, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or the
internal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes High. Output enable
(OE
) and direction (DIR) and select (SAB, SBA) pins are provided
for bus management.
The 74ALS646-1 and 74ALS648-1 will sink 48mA if the VCC is
limited to 5.0V ±0.25V.
within the ±5% VCC range
OL
ORDERING INFORMATION
TYPE
74ALS646/646-1 140MHz 48mA
74ALS648/648-1 140MHz 54mA
DESCRIPTION
24-pin plastic DIP
24-pin plastic SOL
74ALS646/74ALS646-1
74ALS648/74ALS648-1
TYPICAL
TYPICAL f
ORDER CODE
COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS646N, 74ALS646-1N,
74ALS648N, 74ALS648-1N
74ALS646D, 74ALS646-1D,
74ALS648D, 74ALS648-1D
SUPPLY CURRENT
MAX
(TOTAL)
DRAWING
NUMBER
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
A0 – A7 A inputs 1.0/1.0 20µA/0.1mA
B0 – B7 B inputs 1.0/1.0 20µA/0.1mA
CPAB A-to-B clock input 1.0/1.0 20µA/0.1mA
CPBA B-to-A clock input 1.0/1.0 20µA/0.1mA
SAB A-to-B select input 1.0/1.0 20µA/0.1mA
SBA B-to-A select input 1.0/1.0 20µA/0.1mA
DIR Data flow directional control input 1.0/1.0 20µA/0.1mA
OE Output enable input 1.0/1.0 20µA/0.1mA
A0 – A7, B0 – B7 Data outputs 750/240 15mA/24mA
A0 – A7, B0 – B7 Data outputs (-1 version) 750/480 15mA/48mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
1991 Feb 08 853–1408 01670
2
Philips Semiconductors Product specification
Transceiver/register
PIN CONFIGURATION – 74ALS646/646-1
1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12 13
GND
LOGIC SYMBOL – 74ALS646/646-1
4567891011
V
24
CC
23
CPBA
22
SBA
21
OE
20
B0
19
B1
18
B2
17
B3
16
B4
15
B5
14
B6
B7
SC00118
74ALS646/74ALS646-1
74ALS648/74ALS648-1
PIN CONFIGURATION – 74ALS648/648-1
1
CPAB
2
SAB
3
DIR
4
A0
5
A1
6
A2
7
A3
8
A4
9
A5
10
A6
11
A7
12 13
GND
LOGIC SYMBOL – 74ALS648/648-1
4567891011
V
24
CC
23
CPBA
22
SBA
21
OE
20
B0
19
B
1
18
B
2
17
B3
16
B
4
15
B
5
14
6
B
B
7
SC00119
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
1
SAB
2
DIR
3
SPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
V
= Pin 24
CC
GND = Pin 12
20 19 18 17 16 15 14 13
IEC/IEEE SYMBOL – 74ALS646/646-1
21
3
23
22
1
2
4
5
6
7
8
9
10
11
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
5
4D
1
5
1
7
2
7
SC00120
20
19
18
17
16
15
14
13
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
1
SAB
2
DIR
3
SPBA
23
SBA
22
OE
21
B0 B1 B2 B3 B4 B5 B6 B7
VCC = Pin 24
GND = Pin 12
20 19 18 17 16 15 14 13
IEC/IEEE SYMBOL – 74ALS648/648-1
21
3
23
22
1
2
4
5
6
7
8
9
10
11
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
1
5
4D
1
5
1
7
2
7
SC00121
20
19
18
17
16
15
14
13
1991 Feb 08
SC00122
SC00123
3
Philips Semiconductors Product specification
Transceiver/register
BUS MANAGEMENT FUNCTIONS
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ALS646/646-1 and 74ALS648/648-1.
The select pins determine whether data is stored or transferred
through the device in real time.
The DIR determines which bus will receive data when the OE pin is
Low.
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS B
REAL TIME BUS TRANSFER
BUS A TO BUS B
BUS A BUS A
STORAGE FROM
A, B, OR A AND B
74ALS646/74ALS646-1
74ALS648/74ALS648-1
TRANSFER STORED DATA
TO A AND/OR B
BUS A BUS BBUS BBUS B
OE DIR CPABCPBA SAB SBA
LL X X X L
DIR CPABCPBA SAB SBA
OE
LH X X L X
OE DIR CPABCPBA SAB SBA
XX ↑ XXX
XX X ↑ XX
HX ↑↑XX
DIR CPABCPBA SAB SBA
OE
L L X H or L X H
L H H or L X H X
SF00392
1991 Feb 08
4
Loading...