Philips 74ALS573B, 74ALS574A Technical data
查询N74ALS573供应商
INTEGRATED CIRCUITS
74ALS573B/74ALS574A
Latch flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
Philips Semiconductors Product specification
74ALS573B/74ALS574ALatch/flip-flop
74ALS573B Octal transparent latch (3-State)
74ALS574A Octal D flip-flop (3-State)
FEA TURES
•74ALS573B is broadside pinout version of 74ALS373
•74ALS574A is broadside pinout version of 74ALS374
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•Useful as an input or output port for microprocessors
•3-State outputs for bus interfacing
•Common output enable
•74ALS563A and 74ALS564A are inverting version of 74ALS573B
and 74ALS574A respectively
DESCRIPTION
The 74ALS573B is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
The 74ALS573B is functionally identical to the 74ALS373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 74ALS574A is functionally identical to the 74ALS374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
) control gates.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE
independent of the latch operation. When OE
transparent data appears at the output.
When OE
which means they will neither drive nor load the bus.
is High, the outputs are in high impedance “off” state,
TYPICAL
TYPE
74ALS573B 5.0ns 12mA
74ALS574A 6.0ns 15mA
PROPAGATION
DELA Y
) control gates.
) controls all eight 3-State buffers
is Low, latched or
TYPICAL
SUPPLY CURRENT
(TOTAL)
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
V
DESCRIPTION
20-pin plastic DIP 74ALS573BN, 74ALS574AN SOT146-1
20-pin plastic SOL 74ALS573BD, 74ALS574AD SOT163-1
20-pin plastic SSOP
Type II
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS573BDB,
74ALS574ADB
DRAWING
NUMBER
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D7 Data inputs 1.0/1.0 20µA/0.2mA
E (74ALS573B) Latch enable input 1.0/1.0 20µA/0.1mA
OE Output Enable input (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS574A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA
Q0 – Q7 Data outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
1991 Feb 08 853–1307 01670
2
Philips Semiconductors Product specification
74ALS573B/74ALS574ALatch/flip-flop
PIN CONFIGURATION – 74ALS573B
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20
19
18
17
16
15
14
13
12
LOGIC SYMBOL – 74ALS573B
345678
2
11 E
1
D0 D1Q1D2
OE
Q0
Q2 Q3D3Q4D4Q5
D5
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
CC
D7
Q6D6Q7
9
SF01073
PIN CONFIGURATION – 74ALS574A
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
GND
10 11
20
19
18
17
16
15
14
13
12
LOGIC SYMBOL – 74ALS574A
345678
2
11 CP
1
OE
D0 D1Q1D2
Q0
Q2 Q3D3Q4D4Q5
D5
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
CC
SF01074
9
D7
Q6D6Q7
VCC=Pin 20
GND=Pin 10
IEC/IEEE SYMBOL – 74ALS573B
1
11
2
3
4
5
6
7
8
9
EN1
EN2
2D
1
141516171819
1213
SF01075
VCC=Pin 20
GND=Pin 10
141516171819
1213
SF01076
IEC/IEEE SYMBOL – 74ALS574A
1
11
19
18
17
16
15
14
13
12
SF01077
2
3
4
5
6
7
8
9
EN1
C2
2D
1
19
18
17
16
15
14
13
12
SF01078
1991 Feb 08
3
Philips Semiconductors Product specification
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74ALS573B/74ALS574ALatch/flip-flop
LOGIC DIAGRAM – 74ALS573B
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
V
= Pin 20
CC
GND = Pin 10
E
OE
D
Q
E
11
1
Q0
D
Q
E
19
Q1
D
Q
E
18
Q2
D
Q
E
17
Q3
D
E
16
D
Q
E
15
Q4
FUNCTION T ABLE – 74ALS573B
INPUTS
OE E Dn
OUTPUTS
REGISTER
L H L L L
L H H H H
L ↓ l L L
L ↓ h H H
L L X NC NC Hold
H L X NC Z
H H Dn Dn Z
H = High-voltage level
h = High state must be present one setup time before the High-to-Low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low enable transition
INTERNAL
Q0 – Q7
Q5
D
Q
E
14
Q
Q6
D
Q
E
13
12
Q7
SC00109
p
LOGIC DIAGRAM – 74ALS574A
VCC = Pin 20
GND = Pin 10
1991 Feb 08
CP
OE
D0
2
D
CP
11
1
D1
3
Q0
D
CP
19
Q
D2
4
Q1
D
CP
18
Q
D3
5
Q2
D
CP
17
Q
D4
6
Q
16
Q3
D
CP
D5
7
D
Q
CP
15
Q4
D6
8
Q5
D
CP
14
Q
D7
9
Q6
D
Q
CP
13
Q7
12
SC00110
Q
4
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