Philips 74ALS564AN, 74ALS564AD, 74ALS563AD Datasheet
INTEGRATED CIRCUITS
74ALS563A/74ALS564A
Latch flip/flop
Product specification
IC05 Data Handbook
1996 Jul 01
Philips Semiconductors Product specification
74ALS563A/74ALS564ALatch/flip-flop
74ALS563A Octal transparent latch, inverting (3-State)
74ALS564A Octal D flip-flop, inverting (3-State)
FEA TURES
•74ALS563A is broadside pinout and inverting version of
74ALS373
•74ALS564A is broadside pinout and inverting version of
74ALS374
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•Useful as an input or output port for microprocessors
•3-State outputs for bus interfacing
•Common output enable
•74ALS573A and 74ALS574A are non-inverting version of
74ALS563B and 74ALS564A respectively
TYPE
74ALS563A 6.0ns 12mA
74ALS564A 6.0ns 15mA
TYPICAL
PROPAGATION DELAY
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
20-pin plastic DIP 74ALS563AN, 74ALS564AN SOT146-1
20-pin plastic SOL 74ALS563AD, 74ALS564AD SOT163-1
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
TYPICAL
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER
DESCRIPTION
The 74ALS563A is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
The 74ALS563A is a complementary version of the 74ALS373 and
has a broadside pinout configuration to facilitate PC board layout
and allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the inverted data that is present
one setup time before the High-to-Low enable transition.
The 74ALS564A is a complementary version of the 74ALS373 and
has a broadside pinout configuration to facilitate PC board layout
and allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE
independent of the latch operation. When OE
transparent data appears at the output.
When OE
which means they will neither drive nor load the bus.
is High, the outputs are in high impedance “off” state,
) control gates.
) controls all eight 3-State buffers
) control gates.
is Low, latched or
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA
E (74ALS563A) Enable input 1.0/1.0 20µA/0.1mA
OE Output enable input (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS564A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA
Q0 – Q7 Data outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1996 Jul 01 853–1306 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Philips Semiconductors Product specification
74ALS563A/74ALS564ALatch/flip-flop
PIN CONFIGURATION – 74ALS563A
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20
19
18
17
16
15
14
13
12
LOGIC SYMBOL – 74ALS563A
345678
2
11 E
1
D0 D1Q1D2
OE
Q0
Q2 Q3D3Q4D4Q5
D5
V
CC
Q0
Q
1
Q2
Q
3
Q
4
Q
5
Q
6
Q
7
E
D7
Q6D6Q7
PIN CONFIGURATION – 74ALS564A
SC00111
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10 11
GND
20
V
CC
Q0
19
18
Q
1
17
Q2
16
Q
3
15
Q
4
14
Q
5
13
Q
6
12
Q
7
CP
SF01052
LOGIC SYMBOL – 74ALS564A
345678
9
11 CP
1
2
D0 D1Q1D2
OE
Q0
D5
Q2 Q3D3Q4D4Q5
9
D7
Q6D6Q7
VCC=Pin 20
GND=Pin 10
IEC/IEEE SYMBOL – 74ALS563A
1
11
2
3
4
5
6
7
8
9
EN1
EN2
2D
1
141516171819
1213
SC00112
VCC=Pin 20
GND=Pin 10
141516171819
1213
SF01053
IEC/IEEE SYMBOL – 74ALS564A
1
11
19
18
17
16
15
14
13
12
SC00113
2
3
4
5
6
7
8
9
EN1
2D
C2
1
19
18
17
16
15
14
13
12
SF01054
1996 Jul 01
3
Philips Semiconductors Product specification
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74ALS563A/74ALS564ALatch/flip-flop
LOGIC DIAGRAM – 74ALS563A
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
V
= Pin 20
CC
GND = Pin 10
E
OE
D
Q
E
11
1
D
Q
E
19
Q0
D
Q
E
18
Q1
D
Q
E
17
Q2
D
Q
E
16
Q3
15
Q4
FUNCTION T ABLE – 74ALS563A
INPUTS
OE E Dn
OUTPUTS
REGISTER
L H L L H
L H H H L
L ↓ l L H
L ↓ h H L
L L X NC NC Hold
H L X NC Z
H H Dn Dn Z
H = High voltage level
h = High state must be present one setup time before the High-to-Low enable transition
L = Low voltage level
l = Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low enable transition
INTERNAL
Q0 – Q7
D
Q
E
D
E
14
Q5
D
Q
Q6
Q
E
13
12
Q7
SC00116
p
1996 Jul 01
4
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