Philips 74als373 374 DATASHEETS
INTEGRATED CIRCUITS
74ALS373/74ALS374
Latch/flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
Philips Semiconductors Product specification
74ALS373/74ALS374Latch/flip-flop
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
FEA TURES
•8-bit transparent latch – 74ALS373
•8-bit positive edge triggered register – 74ALS374
•3-State output buffers
•Common 3-State output register
•Independent register and 3-State buffer operation
TYPE
74ALS373 6.0ns 14mA
TYPE
74ALS374 50MHz 17mA
TYPICAL
PROPAGATION DELAY
TYPICAL
f
MAX
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1
20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1
20-pin plastic SSOP
Type II
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS373DB, 74ALS374DB SOT339-1
TYPICAL
SUPPLY CURRENT
(TOTAL)
TYPICAL
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
) control gates.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D7 Data inputs 1.0/1.0 20µA/0.1mA
E (74ALS373) Enable input (active-High) 1.0/1.0 20µA/0.1mA
OE Output enable inputs (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS374) Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
Q0 – Q7 3-State outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08 853–1243 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Philips Semiconductors Product specification
74ALS373/74ALS374Latch/flip-flop
PIN CONFIGURATION – 74ALS373
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10 11
GND
V
20
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
E
LOGIC SYMBOL – 74ALS373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
E
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
PIN CONFIGURATION – 74ALS374
CC
SF00250
1
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10 11
GND
V
20OE
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
CP
SF00253
LOGIC SYMBOL – 74ALS374
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
OE
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
= Pin 20
V
CC
GND = Pin 10
IEC/IEEE SYMBOL – 74ALS373
1
11
3
4
7
8
13
14
17
18
EN1
EN2
2D
1
2 5 6 9 12 15 16 19
= Pin 20
V
CC
SF00251
GND = Pin 10
SF00254
IEC/IEEE SYMBOL – 74ALS374
1
11
2
5
6
9
12
15
16
19
SF00252
3
4
7
8
13
14
17
18
EN1
2D
C1
1
2
5
6
9
12
15
16
19
SC00098
1991 Feb 08
3
Philips Semiconductors Product specification
INTERNAL REGISTER
OPERATING MODE
Enable and read register
Latch and read register
Disable outputs
74ALS373/74ALS374Latch/flip-flop
LOGIC DIAGRAM – 74ALS373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
V
= Pin 20
CC
GND = Pin 10
E
OE
D
Q
E
11
1
Q0
D
Q
E
2
Q1
D
Q
E
5
Q2
D
Q
E
6
Q3
D
E
9
D
Q
E
12
Q4
FUNCTION T ABLE – 74ALS373
INPUTS
OE E Dn
L H L L L
L H H H H
L ↓ l L L
L ↓ h H H
L L X NC NC Hold
H L X NC Z
H H Dn Dn Z
H = High-voltage level
h = High state must be present one setup time before the High-to-Low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low enable transition
OUTPUTS
Q0 – Q7
Q5
D
E
15
Q
D
Q
Q6
Q
E
16
19
Q7
SF00256
p
1991 Feb 08
4
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