Philips 74als245a DATASHEETS
INTEGRATED CIRCUITS
74ALS245A/74ALS245A–1
Octal transceiver (3–State)
Product specification
IC05 Data Handbook
1991 Jun 03
Philips Semiconductors Product specification
74ALS245A/74ALS245A-1Octal transceiver (3-State)
FEA TURES
•Octal bidirectional bus interface
•3-State buffer outputs sink 24mA and source 15mA
•Outputs are placed in high impedance state during power-off
conditions
•The -1 version sinks 48mA
DESCRIPTION
The 74ALS245A is an octal transceiver featuring non-inverting
3-State bus compatible outputs in both transmit and receive
directions. The device features an output enable (OE
cascading and transmit/receive (R/T
) input for direction control.
The 74ALS245A-1 is the same as the 74ALS245A except that both
ports sink 48mA within the ±5% V
CC
range.
TYPICAL
TYPE
PROPAGATION
DELA Y
74ALS245A 7.0ns 34mA
74ALS245A-1 7.0ns 34mA
) input for easy
TYPICAL
SUPPLY CURRENT
(TOTAL)
PIN CONFIGURATION
1
T/R
2
A0
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10 11
GND
ORDERING INFORMA TION
ORDER CODE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP
Type II
COMMERCIAL RANGE
V
CC
T
= 0°C to +70°C
amb
74ALS245AN,
74ALS245A-1N
74ALS245AD,
744ALS245A-1D
74ALS245ADB,
74ALS245A-1DB
V
20
19
OE
18
B0
17
B1
16
B2
15
B3
14
B4
13
B5
12
B6
B7
= 5V ±10%,
CC
SF00198
DRAWING
NUMBER
SOT146-1
SOT163-1
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
A0 – A7, B0 – B7 Data inputs 1.0/1.0 20µA/0.1mA
OE Output Enable input (active-Low) 1.0/1.0 20µA/0.1mA
T/R Transmit/receive input 1.0/1.0 20µA/0.1mA
A0 – A7 A port outputs 750/240 15mA/24mA
B0 – B7 B port outputs 750/240 15mA/24mA
A0 – A7 A port outputs (-1 version) 750/480 15mA/48mA
B0 – B7 B port outputs (-1 version) 750/480 15mA/48mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOAD VALUE
HIGH/LOW
1991 Jun 03 853–001 1 02709
2
Philips Semiconductors Product specification
OUTPUTS
74ALS245A/74ALS245A-1Octal transceiver (3-State)
LOGIC SYMBOL
234
A0 A1 A2 A3 A4 A5
19
1
V
= Pin 20
CC
GND = Pin 10
OE
T/R
B0
18
LOGIC DIAGRAM
19
OE
1
T/R
VCC = Pin 20
GND = Pin 10
B2 B3 B4 B5
B1
16 15 14 13
17
567
IEC/IEEE SYMBOL
89
A6 A7
B6 B7
12 11
SF00199
A0 A1 A2 A3 A4 A5 A6 A7
23456789
18
B0
17
B1
16
B2
15
B3
19
1
2
3
4
5
6
7
8
9
14
B4
G3
3EN1 [BA]
3EN2 [AB]
∇ 1
13
B5
2 ∇
12
B6
18
17
16
15
14
13
12
11
11
B7
SC00097
SF00201
FUNCTION TABLE
INPUTS
OE T/R
L L Bus B data to Bus A
L H Bus A data to Bus B
H X Z
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
1991 Jun 03
3
Loading...