Philips 74als175 DATASHEETS

INTEGRATED CIRCUITS

74ALS175

Quad D flip–flop

Product specification
IC05 Data Handbook

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1991 Feb 08

Philips Semiconductors Product specification

74ALS175Quad D flip-flop

FEA TURES

•Four edge-triggered D flip-flops

•Buffered common clock

•Buffered asynchronous master reset

•True and complementary outputs

DESCRIPTION

The 74ALS175 is a quad, edge-triggered D-type flip-flops with
individual D inputs and both Q and Q
clock (CP) and master reset (MR
flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.

All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR
applications where both true and complement outputs are required,
and the clock and master reset are common to all storage elements.

TYPE

TYPICAL

f

MAX

74ALS175 70MHz 7mA

outputs. The common buffered

) inputs load and reset (clear) all

input. The device is useful for

TYPICAL

SUPPLY CURRENT

(TOTAL)

PIN CONFIGURATION

MR

GND

Q0
Q0
D0
D1
Q
Q1

1
2
3
4
5
6

1

16

V

CC

Q3

15

Q3

14

D3

13

D2

12

Q

11

2

107

Q2

98

CP

ORDERING INFORMA TION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

V

= 5V ±10%,

CC

T

= 0°C to +70°C

amb

16-pin plastic DIP 74ALS175N SOT38-4

16-pin plastic SO 74ALS175D SOT109-1

DRAWING

NUMBER

SF00718

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

D0 – D3 Data inputs 1.0/1.0 20µA/0.1mA

CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.1mA

MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA
Q0 – Q3 True outputs 20/80 0.4mA/8mA
Q0 – Q3 Complementary outputs 20/80 0.4mA/8mA

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

9
1

VCC = Pin 16
GND = Pin 8

4 5 12 13

D0 D1 D2 D3

CP
MR

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

2 3 7 6 10 11 15 14

SF00719

IEC/IEEE SYMBOL

74ALS (U.L.)

HIGH/LOW

1
9

4

5

12

13

R

C1

1D

LOAD VALUE

HIGH/LOW

2
3
7

6
10
11

15
14

SF00720

1991 Feb 08 853–1024 01670

2

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

74ALS175Quad D flip-flop

LOGIC DIAGRAM

= Pin 16

V

CC

GND = Pin 8

CP

MR

D0

9

1

4

DQ

CP

RD

D1

5

DQ

CP

RD

32 6 1110 14157

Q

0Q0 Q1Q1 Q2Q2 Q3Q3

D2

12

DQ

CP

RD

D3

13

DQ

FUNCTION TABLE

INPUTS OUTPUTS

MR CP D Q

n

Q

n

L X X L H Reset (clear)
H ↑ h H L Load “1”
H ↑ I L H Load “0”

NOTES:

H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

T

amb

T

stg

Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 16 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C

PARAMETER RATING UNIT

CP

RD

Q

OPERATING

MODE

CC

SF00721

V

RECOMMENDED OPERATING CONDITIONS

V

CC

V
V

I

IK

I

OH

I

OL

T

amb

1991 Feb 08

Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

Input clamp current –18 mA
High-level output current –0.4 mA
Low-level output current 8 mA
Operating free-air temperature range 0 +70 °C

LIMITS

MIN NOM MAX

3