Philips 74als174 DATASHEETS
INTEGRATED CIRCUITS
74ALS174
Hex D flip–flop
Product specification 1991 Feb 08
IC05 Data Handbook
Philips Semiconductors Product specification
74ALS174Hex D flip-flop
FEA TURES
•Four edge-triggered D flip-flops
•Buffered common clock
•Buffered asynchronous master reset
DESCRIPTION
The 74ALS174 has six edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
and master reset (MR
simultaneously .
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR
applications where true outputs only are required, and the clock and
master reset are common to all storage elements.
TYPE
74ALS174 70MHz 7mA
) inputs load and reset (clear) all flip-flops
input. The device is useful for
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
PIN CONFIGURATION
MR
Q0
D0
D1
Q1
D2
Q2
1
2
3
4
5
6
16
15
14
13
12
11
107
98GND CP
V
Q5
D5
D4
Q4
D3
Q3
CC
ORDERING INFORMA TION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
16-pin plastic DIP 74ALS174N SOT38-4
16-pin plastic SO 74ALS174D SOT109-1
DRAWING
NUMBER
SF00188
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D3 Data inputs 1.0/1.0 20µA/0.1mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
MR Master Reset input (active-Low) 1.0/1.0 20µA/0.1mA
Q0 – Q5 Data outputs 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
9
1
V
= Pin 16
CC
GND = Pin 8
346
D0 D1 D2 D3 D4 D5
CP
MR
Q2 Q3 Q4 Q5
Q1
7101215
5Q02
11 13 14
SF00189
IEC/IEEE SYMBOL
74ALS (U.L.)
HIGH/LOW
9
1
3
4
6
11
13
14
R
1D
C1
LOAD VALUE
HIGH/LOW
2
5
7
10
12
15
SF00190
1991 Feb 08 853–1023 01670
2
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
74ALS174Hex D flip-flop
LOGIC DIAGRAM
V
= Pin 16
CC
GND = Pin 8
CP
MR
D0
3
D
CP
R
D
9
1
D1
4
Q0
D
CP
R
D
2
Q
D2
6
Q1
D
CP
R
D
5
Q
D3
Q
7
Q2
FUNCTION TABLE
INPUTS OUTPUTS
MR CP D Q
L X X L Reset (clear)
H ↑ h H Load “1”
H ↑ I L Load “0”
NOTES:
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
n
11
D
CP
R
D
D4
13
Q3
D
CP
R
D
10
Q
D5
14
Q4
D
Q
CP
R
D
12
15
Q5
SF00192
Q
OPERATING
MODE
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage –0.5 to +7.0 V
Input voltage –0.5 to +7.0 V
Input current –30 to +5 mA
Voltage applied to output in High output state –0.5 to V
Current applied to output in Low output state 16 mA
Operating free-air temperature range 0 to +70 °C
Storage temperature range –65 to +150 °C
PARAMETER RATING UNIT
RECOMMENDED OPERATING CONDITIONS
V
T
V
V
I
I
OH
I
OL
amb
CC
IK
Supply voltage 4.5 5.0 5.5 V
High-level input voltage 2.0 V
IH
Low-level input voltage 0.8 V
IL
Input clamp current –18 mA
High-level output current –0.4 mA
Low-level output current 8 mA
Operating free-air temperature range 0 +70 °C
CC
LIMITS
MIN NOM MAX
V
1991 Feb 08
3
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