Philips 74ALS163BN, 74ALS163BDB, 74ALS163BD, 74ALS161BN, 74ALS161BD Datasheet
INTEGRATED CIRCUITS
74ALS161B/74ALS163B
4-bit binary counter
Product specification 1991 Feb 08
IC05 Data Handbook
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
74ALS161B 4-bit binary counter, asynchronous reset
74ALS163B 4-bit binary counter, synchronous reset
FEA TURES
•Synchronous counting and loading
•Two count enable inputs for n-bit cascading
•Positive edge-triggered clock
•Asynchronous reset (74ALS161B)
•Synchronous reset (74ALS163B)
•High speed synchronous expansion
•Typical count rate of 140MHz
TYPICAL
TYPE
74ALS161B 140MHz 10mA
74ALS163B 140MHz 10mA
TYPICAL f
MAX
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
16-pin plastic DIP 74ALS161BN, 74ALS163BN SOT38-4
16-pin plastic SO 74ALS161BD, 74ALS163BD SOT109-1
16-pin plastic SSOP
Type II
V
= 5V ±10%,
CC
T
= 0°C to +70°C
amb
74ALS161BDB,
74ALS163BDB
SUPPLY CURRENT
(TOTAL)
DRAWING
NUMBER
SOT338-1
DESCRIPTION
Synchronous presettable 4-bit binary counters (74ALS161B,
74ALS163B) feature an internal carry look-ahead and can be used
for high speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the parallel enable (PE
action and causes the data at the D0 – D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE
regardless of the levels at count enable (CEP, CET) inputs.
A Low level at the master reset (MR
of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of
the levels at CP, PE
asynchronous clear function).
For the 74ALS163B the clear function is synchronous. A Low level
at the synchronous reset (SR
flip-flops (Q0 – Q3) to Low levels after the next positive-going
transition on the clock (CP) input ( provided that the setup and hold
time requirements for SR
the levels at CP, PE
feature enables the designer to modify the maximum count with only
one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both count enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2).
The TC output is subjected to decoding spikes due to internal race
conditions, Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
, CET and CEP inputs (thus providing an
are met). This action occurs regardless of
, CET and CEP inputs. The synchronous reset
) input disables the counting
are met). Preset takes place
) input sets all the four outputs
) input sets all four outputs of the
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
D0 – D3 Data inputs 1.0/1.0 20µA/0.1mA
CEP Count enable parallel input (active-Low) 1.0/1.0 20µA/0.1mA
CET Count enable trickle input (active-Low) 1.0/1.0 20µA/0.1mA
CP Clock input (active rising edge) 1.0/1.0 20µA/0.1mA
PE Parallel enable input (active-Low) 1.0/1.0 20µA/0.1mA
MR Asynchronous master reset input (active-Low) for 74ALS161B 1.0/1.0 20µA/0.1mA
SR Asynchronous reset input (active-Low) for 74ALS163B 1.0/1.0 20µA/0.1mA
Q0 – Q3 Flip-flop outputs 20/80 0.4mA/8mA
TC T erminal count output (active-Low) 20/80 0.4mA/8mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08 853–1350 01670
2
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
STATE DIAGRAM
0 1 2 3
15
14
13
12 11 10 9
APPLICATIONS
CLOCK
4
5
6
7
8
SF00664
V
CC
D3D0
D1 D2
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
TC74ALS163B
Figure 1. Maximum Count Modifying Scheme
Terminal Count = 6
H H = Enable count
or
L L = Disable count
CP
PE
CEP
74ALS163B
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
Figure 2. Synchronous Multistage Counting Scheme
SC00086
D1 D2 D3D0
74ALS163B 74ALS163B 74ALS163B 74ALS163B
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2 D3D0
TC
PE
CEP
CET
CP
SR
Q0 Q1 Q2 Q3
D1 D2
D3D0
TC
SC00087
1991 Feb 08
3
Philips Semiconductors Product specification
74ALS161B/74ALS163B4-bit binary counter
PIN CONFIGURATION – 74ALS161B
MR
CP
CEP
1
2
D0
3
D1
4
D2
5
6
D3
16
15
14
13
12
11
107
98GND PE
V
TC
Q0
Q1
Q2
Q3
CET
LOGIC SYMBOL – 74ALS161B
34
9
7
10
2
1MR
PE
CEP
CET
CP
Q0 Q1
D1 D2
Q2 Q3
56
D3D0
TC 15
PIN CONFIGURATION – 74ALS163B
1
CC
SF00656
SR
CP
CEP
2
D0
3
D1
4
D2
5
6
D3
16
15
14
13
12
11
107
98GND PE
V
TC
Q0
Q1
Q2
Q3
CET
CC
SF00657
LOGIC SYMBOL – 74ALS163B
34
9
7
10
2
1SR
PE
CEP
CET
CP
Q0 Q1
D1 D2
56
D3D0
TC 15
Q2 Q3
= Pin 16
CC
GND = Pin 8
14 13
12 11V
IEC/IEEE SYMBOL – 74ALS161B
1
9
7
10
2
3
4
5
6
R
M1
G3
G4
C2 /1,3,4+
1
,2 D
CTR DIV 16
4 CT=15
12 11V
SF00659
SF00658
= Pin 16
CC
GND = Pin 8
14 13
IEC/IEEE SYMBOL – 74ALS163B
1
9
7
10
2
14
13
12
11
15
SF00660
3
4
5
6
2R
M1
G3
G4
C2 /1,3,4+
1
,2 D
CTR DIV 16
4 CT=15
14
13
12
11
15
SF00661
1991 Feb 08
4
Philips Semiconductors Product specification
OPERATING MODE
Parallel load
Hold (do nothing)
74ALS161B/74ALS163B4-bit binary counter
LOGIC DIAGRAM – 74ALS161B
2
CP
1
MR
9
PE
10
CET
7
CEP
3
D0
4
D1
R
DCPQ
R
DCPQ
14
Q
Q0
Q
5
D2
D3
VCC = Pin 16
GND = Pin 8
6
R
DCPQ
R
DCPQ
Q
Q
MODE SELECTION FUNCTION TABLE – 74ALS161B
INPUTS OUTPUTS
MR CP CEP CET PE Dn Qn TC
L X X X X X L L Reset (clear)
H ↑ X X l l L L
H ↑ X X l h H (a)
H ↑ h h h X count (a) Count
h X l X h X qn (a)
h X X l h X qn L
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
(a) = The output is High when CET is High and the counter is at terminal count (HHHH)
↑ = Low-to-High clock transition
13
Q1
12
Q2
11
Q3
15
TC
SF00662
1991 Feb 08
5
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