Philips 74AHCT595 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC595; 74AHCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
File under Integrated Circuits, IC06
2000 Mar 15
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than V
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and from−40 to +125 °C.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
CC
74AHC595; 74AHCT595
DESCRIPTION
The 74AHC/AHCT595 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT595 is an 8-stage serial shift register
with a storage register and 3-state outputs. The shift
register has separate clocks.
Data is shifted on the positive-going transitions of the
SHCPinput. The data in eachregisteris transferred to the
storage register on a positive-going transition of the ST
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standardoutput (Q7’)for cascading. It is alsoprovidedwith
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
CP
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
propagation delay CL= 15 pF; VCC=5V
SH
to Q7’ 4.0 3.8 ns
CP
ST
to Q
CP
n
MR to Q7’ 4.4 4.6 ns
C
f
C
I
max
PD
input capacitance 3.0 3.0 pF
maximum clock frequency 170 170 MHz
power dissipation capacitance CL= 50 pF; f = 1 MHz; notes 1, 2 and 3 180 190 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
3. All 9 outputs switching.
TYPICAL
UNIT
AHC AHCT
4.2 4.0 ns
2000 Mar 15 2
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
FUNCTION TABLE
See note 1.
INPUT OUTPUT
SH
CP
ST
OE MR D
CP
Q7’Q
S
n
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high impedance
OFF-state.
↑ XLHHQ
’ NC logic HIGH level shifted into shift register stage 0.
6
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’).
X ↑ LHXNCQ
’ contents of shift register stages (internal Qn’) are
n
transferred to the storage register and parallel output
stages
↑↑LHXQ
’Q
6
’ contents of shift register shifted through. Previous
n
contents of the shift register is transferred to the storage
register and the parallel output stages.
FUNCTION
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition;
X = don’t care;
NC = no change;
Z = high impedance OFF-state.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
74AHC595D −40 to +125 °C 16 SO plastic SOT109-1
74AHC595PW 16 TSSOP plastic SOT403-1
74AHCT595D 16 SO plastic SOT109-1
74AHCT595PW 16 TSSOP plastic SOT403-1
2000 Mar 15 3
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
74AHC595; 74AHCT595
register with output latches; 3-state
PINNING
PIN SYMBOL DESCRIPTION
1, 2, 3, 4, 5, 6, 7 and 15 Q
, Q2, Q3, Q4, Q5, Q6, Q7 and Q
1
8 GND ground (0 V)
9Q
10
11 SH
12 ST
13
14 D
16 V
’ serial data output
7
MR master reset (active LOW)
CP
CP
OE output enable input (active LOW)
S
CC
parallel data output
0
shift register clock input
storage register clock input
serial data input
DC supply voltage
handbook, halfpage
Q
Q
Q
Q
Q
Q
Q
GND
1
1
2
2
3
3
4
4
5
6
7
595
5
6
7
8
16
15
14
13
12
11
10
MNA551
Fig.1 Pin configuration.
handbook, halfpage
V
CC
Q
0
D
S
OE
ST
CP
SH
CP
MR
Q7'
9
14
SH
D
S
11 12
ST
CP
OEMR
CP
Q7'
Q
Q
Q
Q
Q
Q
Q
Q
1310
0
1
2
3
4
5
6
7
9
15
1
2
3
4
5
6
7
MNA552
Fig.2 Logic symbol.
2000 Mar 15 4
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, halfpage
13
12
10
R
11
C1/
14
1D 2D
SRG8
EN3
C2
3
MNA553
15
1
2
3
4
5
6
7
9
handbook, halfpage
D
14
SH
11
MR
10
ST
12
13
OE
74AHC595; 74AHCT595
S
CP
8-STAGE SHIFT REGISTER
CP
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q
Q
Q
Q
Q
Q
Q
0
151234567
3
2
1
6
4
5
Q7'
9
Q
7
MNA554
handbook, full pagewidth
D
S
SH
CP
MR
ST
CP
OE
Fig.3 IEC logic symbol.
STAGE 0 STAGES 1 TO 6 STAGE 7
DCPQ
FF0
R
DCPQ
LATCH
Fig.4 Functional diagram.
DQ
DCPQ
FF7
R
DCPQ
LATCH
Q
'
7
Q
0
Q
Q
1
2
Fig.5 Logic diagram.
2000 Mar 15 5
Q
Q
Q
3
Q
4
5
6
Q
MNA555
7
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
handbook, full pagewidth
SH
ST
CP
D
CP
MR
OE
Q
Q
Q
Q
Q7’
S
0
1
6
7
74AHC595; 74AHCT595
Z-state
Z-state
Z-state
Z-state
MNA556
Fig.6 Timing diagram.
2000 Mar 15 6
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