Philips 74AHC574, 74AHCT574 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC574; 74AHCT574
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
File under Integrated Circuits, IC06
1999 Jun 16
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FEATURES
• 3-state non-inverting outputs for
bus oriented applications
• 8-bit positive, edge-triggered
register
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Independent register and 3-state
buffer operation
• Common 3-state output enable
input
• Output capability; bus driver
category: MSI
• I
CC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard no. 7A.
The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (
OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
When
of the OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs.
The ‘574’ is functionally identical to the ‘374’, but has a different pinning.
74AHC574;
74AHCT574
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
f
max
C
I
C
O
C
PD
propagation delay CL= 15 pF; VCC= 5 V 4.4 4.4 ns
CP to Q
n
maximum clock frequency CL= 15 pF; VCC= 5 V 130 130 MHz
input capacitance VI=VCCor GND 4.0 4.0 pF
output capacitance 4.0 4.0 pF
power dissipation
capacitance
CL= 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
TYPICAL
UNIT
AHC AHCT
10 12 pF
1999 Jun 16 2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574;
74AHCT574
FUNCTION TABLE
See note 1.
OPERATING MODES
INPUTS
OE CP D
n
INTERNAL
FLIP-FLOPS
Load and read register L ↑ IL L
L↑hH H
Load register and disable outputs H ↑ lL Z
H↑hH Z
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
OUTPUTS
Q0to Q
7
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PINS PACKAGE MATERIAL CODE
PACKAGES
74AHC574D 74AHC574D 20 SO plastic SOT163-1
74AHC574PW 74AHC574PW DH 20 TSSOP plastic SOT360-1
74AHCT574D 74AHCT574D 20 SO plastic SOT163-1
74AHCT574PW 74AHCT574PW DH 20 TSSOP plastic SOT360-1
PINNING
PIN SYMBOL DESCRIPTION
1 OE 3-state output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8 and 9 D
0
to D
7
data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge triggered)
19, 18, 17, 16, 15, 14, 13 and 12 Q
20 V
0
CC
to Q
7
3-state flip-flop outputs
DC supply voltage
1999 Jun 16 3
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
handbook, halfpage
OE
D
D
D
D
D
D
D
D
GND
1
2
0
3
1
4
2
5
3
4
5
6
7
574
6
7
8
9
10
MNA444
V
20
CC
Q
19
0
Q
18
1
Q
17
2
Q
16
3
Q
15
4
Q
14
5
Q
13
6
Q
12
7
CP
11
handbook, halfpage
74AHC574;
74AHCT574
11
2
3
4
5
6
7
8
9
CP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
19
Q
0
18
Q
1
17
Q
2
16
Q
3
15
Q
4
14
Q
5
13
Q
6
12
Q
7
1
MNA445
handbook, halfpage
Fig.1 Pin configuration.
11
C1
1
EN
2
1D
3
4
5
6
7
8
9
MNA446
19
18
17
16
15
14
13
12
handbook, halfpage
2
3
4
5
6
7
8
9
11
1
Fig.2 Logic symbol.
D
0
D
1
D
2
D
3
FF1 to FF8
D
4
D
5
D
6
D
7
CP
OE
3-STATE
OUTPUTS
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
MNA447
19
18
17
16
15
14
13
12
Fig.3 IEC logic symbol.
1999 Jun 16 4
Fig.4 Functional diagram.
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1999 Jun 16 5
handbook, full pagewidth
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
CP
OE
D
0
D
FF1
CP
D
1
Q
D
FF2
CP
Q
0
D
2
Q DQ DQ DQ DQ DQ DQ
FF3
CP
Q
1
D
3
FF4
CP
Q
2
D
4
FF5
CP
Q
3
D
5
FF6
CP
Q
4
D
6
FF7
CP
Q
5
D
7
FF8
CP
Q
6
Q
MNA449
7
74AHCT574
74AHC574;
Fig.5 Logic diagram.
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC574;
74AHCT574
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall
r,tf
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature range
see DC and AC
characteristics per device
VCC= 3.3 V ±0.3 V −−100 −−−ns/V
times except for
Schmitt-trigger
V
=5V±0.5 V −−20 −−20 ns/V
CC
inputs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
input voltage range −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 V or VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature range −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C;
note 2
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
− 500 mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO-packages: above 70 °C the value of P
derates linearly with 8 mW/K.
D
For TSSOP-packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Jun 16 6
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