Philips 74AHC573, 74AHCT573 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC573; 74AHCT573
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
1999 Sep 27
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger
actions
• Common 3-state output enable
input
• Functionally identical to the ‘563’
and ‘373’
• Inputsacceptsvoltageshigherthan
V
CC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT573 are octal D-type transparent latches featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications.
A Latch Enable (LE) input and an Output Enable (OE) input are common to all
latches.
The ‘573’ consists of eight D-typetransparent latcheswith 3-state true outputs.
When LE is HIGH, data at the Dninputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present at the
D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE
is LOW, the contents of the 8 latches are available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the latches.
The ‘573’ is functionally identical to the ‘533’, ‘563’ and ‘373’, but the ‘533’ and
‘563’ have inverted outputs and the ‘563’ and ‘373’ have a different pin
arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
O
C
PD
propagation delay
Dnto Qn; LE to Q
n
input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation
capacitance
CL= 15 pF; VCC= 5 V 4.2 3.9 ns
CL= 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
P
D=CPD
× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
TYPICAL
UNIT
AHC AHCT
12 18 pF
1999 Sep 27 2
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
FUNCTION TABLE
See note 1.
OPERATING MODES
Enable and read register
(transparent mode)
INPUTS
OE LE D
n
INTERNAL
LATCHES
LHLLL
LHHHH
OUTPUTS
Q0to Q
Latch and read register L L I L L
LLhHH
Latch register and disable
outputs
HL l LZ
HLhHZ
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PINS PACKAGE MATERIAL CODE
PACKAGES
74AHC573D 74AHC573D 20 SO plastic SOT163-1
74AHC573PW 74AHC573PW DH 20 TSSOP plastic SOT360-1
74AHCT573D 74AHCT573D 20 SO plastic SOT163-1
74AHCT573PW 7AHCT573PW DH 20 TSSOP plastic SOT360-1
7
PINNING
PIN SYMBOL DESCRIPTION
1
2to9 D
OE 3-state output enable input (active LOW)
0
to D
7
data inputs
10 GND ground (0 V)
11 LE latch enable input (active HIGH)
12 to 19 Q
20 V
7
CC
to Q
0
3-state latch outputs
DC supply voltage
1999 Sep 27 3
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
handbook, halfpage
OE
D
D
D
D
D
D
D
D
GND
1
2
0
3
1
4
2
5
3
4
5
6
7
573
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MNA388
Fig.1 Pin configuration.
V
Q
Q
Q
Q
Q
Q
Q
Q
LE
CC
0
1
2
3
4
5
6
7
handbook, halfpage
11
2
3
4
5
6
7
8
9
LE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
19
Q
0
18
Q
1
17
Q
2
16
Q
3
15
Q
4
14
Q
5
13
Q
6
12
Q
7
1
MNA389
Fig.2 Logic symbol.
handbook, halfpage
11
C1
1
EN
2
1D
3
4
5
6
7
8
9
MNA390
19
18
17
16
15
14
13
12
Fig.3 IEC logic symbol.
1999 Sep 27 4
handbook, halfpage
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
LE
11
OE
1
0
1
2
3
4
5
6
7
LATCH
1 to 8
Fig.4 Functional diagram.
3-STATE
OUTPUTS
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
MNA391
19
18
17
16
15
14
13
12
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
D
4
Q D
Q
3
LATCH
5
D
5
Q D
Q
4
Q D
LATCH
6
D
6
LATCH
Q
5
Q D
7
Q
6
D
7
LATCH
LE
OE
D
0
D
LATCH
LE
D
1
Q
1
D
LATCH
2
LE LE LE LE LE LE LE
Q
0
D
2
Q D
Q
1
LATCH
3
D
3
Q D
Q
2
LATCH
4
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
74AHC 74AHCT
SYMBOL PARAMETER CONDITIONS
MIN. TYP. MAX. MIN. TYP. MAX.
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall rates VCC= 3.3 V ±0.3 V −−100 −−−ns/V
r,tf
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature range
see DC and AC
characteristics per device
V
=5V±0.5 V −−20 −−20
CC
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
0 − V
CC
CC
8
Q
Q
MNA392
UNIT
V
7
1999 Sep 27 5
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of P
For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.
DC supply voltage −0.5 +7.0 V
input voltage range −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink
−0.5V<VO<VCC+ 0.5 V −±25 mA
current
DC VCC or GND current −±75 mA
storage temperature
−65 +150 °C
range
power dissipation per
for temperature range: −40 to +125 °C; note 2 − 500 mW
package
derates linearly with 8 mW/K.
D
1999 Sep 27 6
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