INTEGRATED CIRCUITS
DATA SHEET
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification |
1999 Sep 28 |
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
Octal D-type flip-flop; positive edge-trigger; 3-state |
74AHC374; |
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74AHCT374 |
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FEATURES |
DESCRIPTION |
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· ESD protection: |
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin |
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HBM EIA/JESD22-A114-A |
compatible with low power Schottky TTL (LSTTL). They are specified in |
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exceeds 2000 V |
compliance with JEDEC standard No. 7A. |
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MM EIA/JESD22-A115-A |
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type |
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exceeds 200 V |
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Philips Semiconductors |
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Product specification |
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CDM EIA/JESD22-C101
inputs for each flip-flop and 3-state outputs for bus oriented applications.
exceeds 1000 V
A clock (CP) and an output enable (OE) input are common to all flip-flops.
·Balanced propagation delays
·All inputs have Schmitt-trigger actions
·Inputs accepts voltages higher than
VCC
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
· Common 3-state output enable |
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs. |
input |
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·ICC category: MSI
·For AHC only:
operates with CMOS input levels
·For AHCT only:
operates with TTL input levels
·Specified from
-40 to +85 and +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf £ 3.0 ns.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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AHC |
AHCT |
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tPHL/tPLH |
propagation delay; |
CL = 15 pF; VCC = 5 V |
3.5 |
5.0 |
ns |
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CP to Qn |
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fmax |
maximum clock frequency |
CL = 15 pF; VCC = 5 V |
50 |
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MHz |
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CI |
input capacitance |
VI = VCC or GND |
3.0 |
3.0 |
pF |
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CO |
output capacitance |
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4.0 |
4.0 |
pF |
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CPD |
power dissipation |
CL = 50 pF; f = 1 MHz; |
10 |
12 |
pF |
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capacitance |
notes 1 and 2 |
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Notes
1.CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
å (CL ´ VCC2 ´ fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
1999 Sep 28 |
2 |
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state |
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74AHC374; |
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74AHCT374 |
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FUNCTION TABLE |
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See note 1. |
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OPERATING MODES |
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INPUTS |
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INTERNAL |
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OUTPUTS |
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FLIP-FLOPS |
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OE |
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CP |
Dn |
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Q0 to Q7 |
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Load and read register |
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L |
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− |
I |
L |
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L |
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L |
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− |
h |
H |
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H |
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Load register and |
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H |
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− |
l |
L |
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Z |
disable outputs |
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H |
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− |
h |
H |
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Z |
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Note
1.H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care;
Z = high-impedance OFF-state;
− = LOW-to-HIGH CP transition.
ORDERING INFORMATION
OUTSIDE NORTH |
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NORTH AMERICA |
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PACKAGES |
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AMERICA |
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PINS |
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PACKAGE |
MATERIAL |
CODE |
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74AHC374D |
74AHC374D |
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SO |
plastic |
SOT163-1 |
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74AHC374PW |
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74AHC374PW DH |
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TSSOP |
plastic |
SOT360-1 |
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74AHCT374D |
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74AHCT374D |
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SO |
plastic |
SOT163-1 |
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74AHCT374PW |
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7AHCT374PW DH |
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TSSOP |
plastic |
SOT360-1 |
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PINNING |
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PIN |
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SYMBOL |
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DESCRIPTION |
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1 |
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3-state output enable input (active LOW) |
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OE |
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2, 5, 6, 9, 12, 15, |
Q0 to Q7 |
3-state flip-flop outputs |
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16 and 19 |
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3, 4, 7, 8, 13, 14, |
D0 to D7 |
data inputs |
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17 and 18 |
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10 |
GND |
ground (0 V) |
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11 |
CP |
clock input (LOW-to-HIGH, edge triggered) |
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20 |
VCC |
DC supply voltage |
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1999 Sep 28 |
3 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
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VCC |
OE |
1 |
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20 |
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Q0 |
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Q7 |
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2 |
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19 |
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D0 |
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D7 |
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3 |
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18 |
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D1 |
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D6 |
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4 |
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17 |
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Q1 |
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Q6 |
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5 |
374 |
16 |
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Q2 |
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Q5 |
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6 |
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15 |
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D2 |
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D5 |
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7 |
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14 |
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8 |
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D4 |
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D3 |
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13 |
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Q3 |
9 |
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Q4 |
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12 |
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GND 10 |
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CP |
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11 |
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MNA194 |
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Fig.1 Pin configuration.
handbook, halfpage |
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EN |
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11 |
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C1 |
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3 |
1D |
2 |
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4 |
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5 |
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7 |
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6 |
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8 |
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9 |
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13 |
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12 |
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14 |
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15 |
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17 |
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16 |
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18 |
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19 |
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MNA196 |
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handbook, halfpage |
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11 |
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3 |
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CP |
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D0 |
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Q0 |
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4 |
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5 |
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D1 |
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Q1 |
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7 |
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6 |
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D2 |
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Q2 |
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8 |
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9 |
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D3 |
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Q3 |
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13 |
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12 |
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D4 |
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Q4 |
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14 |
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15 |
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D5 |
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Q5 |
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17 |
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16 |
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D6 |
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Q6 |
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18 |
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19 |
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D7 |
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Q7 |
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OE |
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1 |
MNA195 |
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Fig.2 Logic symbol.
handbook, halfpage
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D0 |
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Q0 |
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4 |
D1 |
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Q1 |
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7 |
D2 |
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Q2 |
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8 |
D3 |
FF1 |
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3-STATE |
Q3 |
9 |
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13 |
D4 |
to |
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Q4 |
12 |
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OUTPUTS |
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FF8 |
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14 |
D5 |
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Q5 |
15 |
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17 |
D6 |
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Q6 |
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18 |
D7 |
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Q7 |
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11 |
CP |
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1 |
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OE |
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MNA197
Fig.3 IEC logic symbol. |
Fig.4 Functional diagram. |
1999 Sep 28 |
4 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger; 3-state |
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74AHC374; |
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74AHCT374 |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
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D7 |
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D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
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CP |
CP |
CP |
CP |
CP |
CP |
CP |
CP |
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FF1 |
FF2 |
FF3 |
FF4 |
FF5 |
FF6 |
FF7 |
FF8 |
CP |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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MNA198 |
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Fig.5 |
Logic diagram. |
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RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
CONDITIONS |
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74AHC |
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74AHCT |
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UNIT |
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MIN. |
TYP. |
MAX. |
MIN. |
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TYP. |
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MAX. |
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VCC |
DC supply voltage |
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2.0 |
5.0 |
5.5 |
4.5 |
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5.0 |
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5.5 |
V |
VI |
input voltage |
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0 |
− |
5.5 |
0 |
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− |
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5.5 |
V |
VO |
output voltage |
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0 |
− |
VCC |
0 |
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− |
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VCC |
V |
Tamb |
operating ambient temperature |
see DC and AC |
−40 |
+25 |
+85 |
−40 |
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+25 |
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+85 |
°C |
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range |
characteristics per |
−40 |
+25 |
+125 |
−40 |
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+25 |
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+125 |
°C |
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device |
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tr,tf ( t/ f) |
input rise and fall rates |
VCC = 3.3 V ±0.3 V |
− |
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100 |
− |
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− |
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− |
ns/V |
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VCC = 5 V ±0.5 V |
− |
− |
20 |
− |
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− |
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20 |
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1999 Sep 28 |
5 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VCC |
DC supply voltage |
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−0.5 |
+7.0 |
V |
VI |
input voltage range |
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−0.5 |
+7.0 |
V |
IIK |
DC input diode current |
VI < −0.5 V; note 1 |
− |
−20 |
mA |
IOK |
DC output diode current |
VO < −0.5 V or VO > VCC + 0.5 V; note 1 |
− |
±20 |
mA |
IO |
DC output source or sink current |
−0.5 V < VO < VCC + 0.5 V |
− |
±25 |
mA |
ICC |
DC VCC or GND current |
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±75 |
mA |
Tstg |
storage temperature range |
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−65 |
+150 |
°C |
PD |
power dissipation per package |
for temperature range: −40 to +125 °C; note 2 |
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500 |
mW |
Notes
1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 28 |
6 |
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