INTEGRATED CIRCUITS
DATA SHEET
74AHC32; 74AHCT32
Quad 2-input OR gate
Product specification |
1999 Sep 27 |
Supersedes data of 1998 Dec 09
File under Integrated Circuits, IC06
Philips Semiconductors |
Product specification |
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Quad 2-input OR gate |
74AHC32; 74AHCT32 |
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FEATURES
·ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
·Balanced propagation delays
·All inputs have Schmitt-trigger actions
·Inputs accepts voltages higher than
VCC
·For AHC only:
operates with CMOS input levels
·For AHCT only:
operates with TTL input levels
·Specified from
-40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT32 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHC/AHCT32 provides the 2-input OR function.
FUNCTION TABLE
See note 1.
INPUT |
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OUTPUT |
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nA |
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nB |
nY |
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L |
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L |
L |
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L |
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H |
H |
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H |
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L |
H |
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H |
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H |
H |
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Note
1.H = HIGH voltage level L = LOW voltage level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf £ 3.0 ns.
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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AHC |
AHCT |
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tPHL/tPLH |
propagation delay |
CL = 15 pF; |
3.5 |
5.0 |
ns |
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nA, nB to nY |
VCC = 5 V |
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CI |
input capacitance |
VI = VCC or GND |
3.0 |
3.0 |
pF |
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CO |
output capacitance |
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4.0 |
4.0 |
pF |
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CPD |
power dissipation |
CL = 50 pF; |
10 |
12 |
pF |
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capacitance |
f = 1 MHz; |
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notes 1 and 2 |
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Notes
1.CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
å (CL ´ VCC2 ´ fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
PINNING
PIN |
SYMBOL |
DESCRIPTION |
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1, 4, 9 and 12 |
1A to 4A |
data inputs |
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2, 5, 10 and 13 |
1B to 4B |
data inputs |
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3, 6, 8 and 11 |
1Y to 4Y |
data outputs |
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7 |
GND |
ground (0 V) |
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14 |
VCC |
DC supply voltage |
1999 Sep 27 |
2 |
Philips Semiconductors |
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Product specification |
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Quad 2-input OR gate |
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74AHC32; 74AHCT32 |
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ORDERING INFORMATION |
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OUTSIDE NORTH |
NORTH AMERICA |
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PACKAGES |
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AMERICA |
PINS |
PACKAGE |
MATERIAL |
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CODE |
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74AHC32D |
74AHC32D |
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SO |
plastic |
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SOT108-1 |
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74AHC32PW |
74AHC32PW DH |
14 |
TSSOP |
plastic |
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SOT402-1 |
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74AHCT32D |
74AHCT32D |
14 |
SO |
plastic |
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SOT108-1 |
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74AHCT32PW |
74AHCT32PW DH |
14 |
TSSOP |
plastic |
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SOT402-1 |
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handbook, halfpage
1A |
1 |
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14 |
VCC |
1B |
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2 |
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13 |
4B |
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1Y |
3 |
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12 |
4A |
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2A |
4 |
32 |
11 |
4Y |
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2B |
5 |
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10 |
3B |
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2Y |
6 |
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9 |
3A |
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GND |
7 |
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8 |
3Y |
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MNA240 |
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Fig.1 Pin configuration.
handbook, halfpage |
1 |
1A |
3 |
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1Y |
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2 |
1B |
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4 |
2A |
6 |
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2Y |
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5 |
2B |
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9 |
3A |
8 |
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3Y |
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10 |
3B |
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12 |
4A |
11 |
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4Y |
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13 |
4B |
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MNA242 |
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handbook, halfpage
A
Y
B
MNA241
Fig.2 Logic diagram (one gate).
handbook, halfpage |
1 |
≥ 1 |
3 |
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2 |
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4 |
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≥ 1 |
6 |
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5 |
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9 |
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≥ 1 |
8 |
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10 |
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12 |
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≥ 1 |
11 |
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13 |
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MNA243 |
Fig.3 Functional diagram. |
Fig.4 IEC logic symbol. |
1999 Sep 27 |
3 |
Philips Semiconductors |
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Product specification |
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Quad 2-input OR gate |
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74AHC32; 74AHCT32 |
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RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
PARAMETER |
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CONDITIONS |
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74AHC |
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74AHCT |
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UNIT |
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MIN. |
TYP. |
MAX. |
MIN. |
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TYP. |
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MAX. |
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VCC |
DC supply voltage |
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2.0 |
5.0 |
5.5 |
4.5 |
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5.0 |
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5.5 |
V |
VI |
input voltage |
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0 |
− |
5.5 |
0 |
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− |
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5.5 |
V |
VO |
output voltage |
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0 |
− |
VCC |
0 |
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− |
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VCC |
V |
Tamb |
operating ambient temperature |
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see DC and AC |
−40 |
+25 |
+85 |
−40 |
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+25 |
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+85 |
°C |
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range |
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characteristics per |
−40 |
+25 |
+125 |
−40 |
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+25 |
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+125 |
°C |
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device |
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tr,tf ( t/ f) |
input rise and fall rates |
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VCC = 3.3 V ±0.3 V |
− |
− |
100 |
− |
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− |
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− |
ns/V |
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VCC = 5 V ±0.5 V |
− |
− |
20 |
− |
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− |
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LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VCC |
DC supply voltage |
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−0.5 |
+7.0 |
V |
VI |
input voltage range |
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−0.5 |
+7.0 |
V |
IIK |
DC input diode current |
VI < −0.5 V; note 1 |
− |
−20 |
mA |
IOK |
DC output diode current |
VO < −0.5 V or VO > VCC + 0.5 V; note 1 |
− |
±20 |
mA |
IO |
DC output source or sink current |
−0.5 V < VO < VCC + 0.5 V |
− |
±25 |
mA |
ICC |
DC VCC or GND current |
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±75 |
mA |
Tstg |
storage temperature range |
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−65 |
+150 |
°C |
PD |
power dissipation per package |
for temperature range: −40 to +125 °C; note 2 |
− |
500 |
mW |
Notes
1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 27 |
4 |
Philips Semiconductors |
Product specification |
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Quad 2-input OR gate |
74AHC32; 74AHCT32 |
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DC CHARACTERISTICS
74AHC family
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
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TEST CONDITIONS |
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Tamb (°C) |
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SYMBOL |
PARAMETER |
OTHER |
VCC (V) |
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25 |
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−40 to +85 |
−40 to +125 |
UNIT |
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MIN. |
TYP. |
MAX. |
MIN. |
MAX. |
MIN. |
MAX. |
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VIH |
HIGH-level input |
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2.0 |
1.5 |
− |
− |
1.5 |
− |
1.5 |
− |
V |
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voltage |
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3.0 |
2.1 |
− |
− |
2.1 |
− |
2.1 |
− |
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5.5 |
3.85 |
− |
− |
3.85 |
− |
3.85 |
− |
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VIL |
LOW-level input |
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2.0 |
− |
− |
0.5 |
− |
0.5 |
− |
0.5 |
V |
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voltage |
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3.0 |
− |
− |
0.9 |
− |
0.9 |
− |
0.9 |
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5.5 |
− |
− |
1.65 |
− |
1.65 |
− |
1.65 |
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VOH |
HIGH-level output |
VI = VIH or VIL; |
2.0 |
1.9 |
2.0 |
− |
1.9 |
− |
1.9 |
− |
V |
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voltage; all |
IO = −50 μA |
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3.0 |
2.9 |
3.0 |
− |
2.9 |
− |
2.9 |
− |
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4.5 |
4.4 |
4.5 |
− |
4.4 |
− |
4.4 |
− |
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HIGH-level output |
VI = VIH or VIL; |
3.0 |
2.58 |
− |
− |
2.48 |
− |
2.40 |
− |
V |
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voltage |
IO = −4.0 mA |
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VI = VIH or VIL; |
4.5 |
3.94 |
− |
− |
3.8 |
− |
3.70 |
− |
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IO = −8.0 mA |
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VOL |
LOW-level output |
VI = VIH or VIL; |
2.0 |
− |
0 |
0.1 |
− |
0.1 |
− |
0.1 |
V |
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voltage; all |
IO = 50 μA |
3.0 |
− |
0 |
0.1 |
− |
0.1 |
− |
0.1 |
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outputs |
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4.5 |
− |
0 |
0.1 |
− |
0.1 |
− |
0.1 |
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LOW-level output |
VI = VIH or VIL; |
3.0 |
− |
− |
0.36 |
− |
0.44 |
− |
0.55 |
V |
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voltage |
IO = 4 mA |
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VI = VIH or VIL; |
4.5 |
− |
− |
0.36 |
− |
0.44 |
− |
0.55 |
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IO = 8 mA |
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II |
input leakage |
VI = VCC or GND |
5.5 |
− |
− |
0.1 |
− |
1.0 |
− |
2.0 |
μA |
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current |
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IOZ |
3-state output |
VI = VIH or VIL; |
5.5 |
− |
− |
±0.25 |
− |
±2.5 |
− |
±10.0 |
μA |
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OFF current |
VO = VCC or GND |
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ICC |
quiescent supply |
VI = VCC or GND; |
5.5 |
− |
− |
2.0 |
− |
20 |
− |
40 |
μA |
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current |
IO = 0 |
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CI |
input capacitance |
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− |
− |
3 |
10 |
− |
10 |
− |
10 |
pF |
1999 Sep 27 |
5 |
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