Philips 74AHCT157 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC157; 74AHCT157
Quad 2-input multiplexer
Product specification
File under Integrated Circuits, IC06
1999 Sep 24
Philips Semiconductors Product specification
Quad 2-input multiplexer
FEATURES
• ESD protection: HBM EIA/JESD22-A114-A
exceeds 2000 V MM EIA/JESD22-A115-A
exceeds 200 V CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Inputs accept voltages higher than V
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and +125 °C.
FUNCTION TABLE
See note 1.
INPUT OUTPUT
ESnI
HXXX L
LLLX L
LLHX H
LHXL L
LHXH H
0nI1
CC
nY
74AHC157;
74AHCT157
DESCRIPTION
The 74AHC/AHCT157 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The74AHC/AHCT157arequad2-inputmultiplexerswhich
select 4 bits of data from two sources under the control of
a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs(1Y to 4Y)
are forced LOW regardless of all other input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the ‘157’. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as a function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The‘157’is the logic implementation ofa4-pole,2-position
switch,where the positionof the switch isdetermine by the
logic levels applied to S.
The logic equations are:
1Y = E × (1I1× S+1I0×S);
2Y = E × (2I1× S+2I0×S);
3Y = E × (3I1× S+3I0×S);
4Y = E × (4I1× S+4I0×S).
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC157D 74AHC157D 16 SO plastic SOT109-1
74AHC157PW 74AHC157PW DH 16 TSSOP plastic SOT403-1
74AHCT157D 74AHCT157D 16 SO plastic SOT109-1
74AHCT157PW 74AHCT157PW DH 16 TSSOP plastic SOT403-1
1999 Sep 24 2
NORTH AMERICA
PINS PACKAGE MATERIAL CODE
The ‘157’ is identical to the ‘158’ but has non-inverting
(true) outputs.
PACKAGES
Philips Semiconductors Product specification
Quad 2-input multiplexer
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
O
C
PD
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
=25°C; tr=tf≤3.0 ns.
amb
propagation delay
nI
,nI1to nY CL= 15 pF; VCC= 5 V 3.2 3.4 ns
0
StonY C
= 15 pF; VCC= 5 V 4.5 5.1 ns
L
EtonY CL= 15 pF; VCC= 5 V 3.7 4.0 ns
input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation
capacitance
CL= 50 pF; f = 1 MHz; notes 1 and 2
4 outputs switching via S 31 41 pF
1 output switching via I 13 16 pF
2
× fi+ ∑ (CL× V
CC
2
× fo) = sum of outputs;
CC
2
× fo) where:
CC
74AHC157;
74AHCT157
TYPICAL
UNIT
AHC AHCT
PINNING
PIN SYMBOL DESCRIPTION
1 S common data select input
2, 5, 11 and 14 1I
3, 6, 10 and 13 1I
0
1
to 4I
to 4I
0
1
data inputs from source 0
data inputs from source 1
4, 7, 9 and 12 1Y to 4Y multiplexer outputs
8 GND ground (0 V)
15
16 V
E enable input (active LOW)
CC
DC supply voltage
1999 Sep 24 3
Philips Semiconductors Product specification
Quad 2-input multiplexer
handbook, halfpage
1I
1I
1Y
2I
2I
2Y
GND
S
1
2
0
3
1
4
157
5
0
6
1
7
8
MNA480
74AHC157;
74AHCT157
V
16
CC
15
E
4I
14
0
4I
13
1
12
4Y
11
3I
0
3I
10
1
3Y
9
handbook, halfpage
1
15
1I
1I
0
S
E
1Y
2I
2I
1
0
2Y
3I
3I
1
0
3Y
131410116532
4I
4I
1
0
1
4Y
12974
MNA481
handbook, halfpage
Fig.1 Pin configuration.
1
G1
15
EN
2
1
3
5
6
11
10
14
13
MUX
1
MNA482
4
7
9
12
handbook, halfpage
1I
2
1I
3
2I
5
2I
6
3I
11
3I
10
4I
14
4I
13
Fig.2 Logic symbol.
0
1
0
1
SELECTOR
0
1
0
1
S
MULTIPLEXER
OUTPUTS
E
151
1Y
2Y
3Y
4Y
MNA483
4
7
9
12
Fig.3 IEC logic symbol.
1999 Sep 24 4
Fig.4 Functional diagram.
Philips Semiconductors Product specification
Quad 2-input multiplexer
handbook, halfpage
S
E
1I
1
1I
0
2I
1
2I
0
3I
1
3I
0
74AHC157;
74AHCT157
1Y
2Y
3Y
4I
1
4I
0
4Y
MNA484
Fig.5 Logic diagram.
1999 Sep 24 5
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