Philips 74ahc ahct273 DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
74AHC273; 74AHCT273
Octal D-type flip-flop with reset;
positive-edge trigger
Product specification
File under Integrated Circuits, IC06
1999 Sep 01
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
FEATURES
• Ideal buffer for MOS microcontroller or memory
• Common clock and master reset
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt trigger actions
• Inputs accepts voltages higher than V
• See ‘377’ for clock enable version
• See ‘373’ for transparent latch version
• See ‘374’ for 3-state version
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
CC
74AHC273; 74AHCT273
DESCRIPTION
The 74AHC/AHCT273 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT273 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs.
Thecommonclock(CP)andmasterreset(MR)inputsload
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
Ground = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
f
max
C
I
C
O
C
PD
propagation delay CL= 15 pF; VCC=5V
CP to Q
MR to Q
n
n
maximum clock frequency CL= 15 pF; VCC= 5 V 120 120 MHz
input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation
capacitance
CL= 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
TYPICAL
UNIT
AHC AHCT
4.2 4.0 ns
3.7 3.9 ns
14.0 18.0 pF
1999 Sep 01 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
74AHC273; 74AHCT273
positive-edge trigger
FUNCTION TABLE
See note 1.
OPERATING MODES
MR CP D
reset (clear) L X X L
load ‘1’ H ↑ hL
load ‘0’ H ↑ lL
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
↑ = LOW-to-HIGH transition.
ORDERING INFORMATION
INPUTS OUTPUTS
n
Q
n
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PINS PACKAGE MATERIAL CODE
PACKAGES
74AHC273D 74AHC273D 20 SO plastic SOT163-1
74AHC273PW 74AHC273PW DH 20 TSSOP plastic SOT360-1
74AHCT273D 74AHCT273D 20 SO plastic SOT163-1
74AHCT273PW 7AHCT273PW DH 20 TSSOP plastic SOT360-1
PINNING
PIN SYMBOL DESCRIPTION
1
2, 5, 6, 9, 12, 15, 16 and 19 Q
3, 4, 7, 8, 13, 14, 17 and 18 D
MR master reset input (active LOW)
0
0
to Q
to D
7
7
flip-flop outputs
data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH; edge-triggered)
20 V
CC
DC supply voltage
1999 Sep 01 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
handbook, halfpage
MR
Q
D
D
Q
Q
D
D
Q
GND
1
2
0
3
0
4
1
5
1
2
2
3
3
273
6
7
8
9
10
MNA459
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
Q
12
4
CP
11
handbook, halfpage
74AHC273; 74AHCT273
11
CP
3
D
0
4
D
1
7
D
2
8
D
3
13
D
4
14
D
5
17
D
6
18
D
7
MR
1
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
MNA460
2
5
6
9
12
15
16
19
handbook, halfpage
Fig.1 Pin configuration.
11
C1
1
R
3
1D
4
7
8
13
14
17
18
MNA461
2
5
6
9
12
15
16
19
handbook, halfpage
Fig.2 Logic symbol.
D
3
0
D
1
4
D
7
2
D
8
D
13
D
14
D
17
D
18
MR
1
CP
11
FF1
3
4
5
6
7
to
FF8
Q
Q
Q
Q
Q
Q
Q
Q
MNA462
2
0
5
1
6
2
9
3
12
4
15
5
16
6
19
7
Fig.3 IEC logic symbol.
1999 Sep 01 4
Fig.4 Functional diagram.
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger
handbook, full pagewidth
CP
MR
D
0
D
CP
FF1
R
D
1
Q
D
D
CP
FF2
R
Q
0
D
2
Q
D
D
CP
FF3
R
Q
1
74AHC273; 74AHCT273
D
3
Q
D
D
CP
FF4
R
Q
2
D
4
Q
D
D
CP
FF5
R
Q
3
D
5
Q
D
D
CP
FF6
R
Q
4
D
6
Q
D
D
CP
FF7
R
Q
5
D
7
Q
D
D
Q
CP
FF8
R
D
Q
6
MNA463
Q
7
Fig.5 Logic diagram.
1999 Sep 01 5
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
74AHC273; 74AHCT273
positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall ratio VCC= 3.3 ±0.3 V −−100 −−−ns/V
r,tf
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature
see DC and AC
characteristics per device
V
=5±0.5 V −−20 −−20
CC
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C;
note 2
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
− 500 mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Sep 01 6
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