INTEGRATED CIRCUITS
DATA SH EET
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Product specification
File under Integrated Circuits, IC06
2000 Apr 03
Philips Semiconductors Product specification
Quad 2-input multiplexer; 3-state
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Non-inverting data path
• Inputs accept voltages higher than V
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT257 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
CC
74AHC257;
74AHCT257
data from two sources and are controlled by a common
data select input (S).
The data inputs from source 0 (1I0to 4I0) are selected
when input S is LOW and the data inputs from source 1
(1I1to 4I1) are selected when S is HIGH.Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The 74AHC/AHCT257 is the logic implementation of a
4-pole2-positionswitch,where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
If OE is LOW then the logic equations for the outputs are:
1Y = 1I1× S+1I0×S;
2Y = 2I1× S+2I0×S;
3Y = 3I1× S+3I0×S;
4Y = 4I1× S+4I0×S.
The ‘257’ is identical to the ‘258’ but has non-inverting
(true) outputs.
The 74AHC/AHCT257 has four identical 2-input
multiplexers with 3-state outputs, which select 4 bits of
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
O
C
PD
propagation delay
nl
,nI1to nY CL= 15 pF; VCC= 5 V 2.9 3.7 ns
0
StonY C
= 15 pF; VCC= 5 V 3.5 5.1 ns
L
input capacitance VI=VCCor GND 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation
capacitance
CL= 50 pF; fi= 1 MHz; notes 1 and 2
4 outputs switching via input S 45 51 pF
1 output switching via input I 15 15 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
TYPICAL
UNIT
AHC AHCT
2000 Apr 03 2
Philips Semiconductors Product specification
Quad 2-input multiplexer; 3-state
FUNCTION TABLE
See note 1.
INPUT OUTPUT
OE S nI
HXXXZ
LHXLL
LHXHH
LLLXL
LLHXH
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high impedance OFF-state.
ORDERING INFORMATION
74AHC257;
74AHCT257
0
nI
1
nY
PACKAGES
TYPE NUMBER
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE
74AHC257D −40 to +125 °C 16 SO plastic SOT109-1
74AHC257PW 16 TSSOP plastic SOT403-1
74AHCT257D 16 SO plastic SOT109-1
74AHCT257PW 16 TSSOP plastic SOT403-1
PINNING
PIN SYMBOL DESCRIPTION
1 S common data select input
2, 5, 11 and 14 1I
3, 6, 10 and 13 1I
0
1
to 4I
to 4I
0
1
data inputs from source 0
data inputs from source 1
4, 7, 9 and 12 1Y to 4Y multiplexer outputs
8 GND ground (0 V)
15
16 V
OE output enable input (active LOW)
CC
DC supply voltage
2000 Apr 03 3
Philips Semiconductors Product specification
Quad 2-input multiplexer; 3-state
handbook, halfpage
1I
1I
1Y
2I
2I
2Y
GND
S
1
2
0
3
1
4
257
5
0
6
1
7
8
MNA536
V
16
CC
OE
15
4I
14
0
4I
13
1
4Y
12
3I
11
0
3I
10
1
3Y
9
handbook, halfpage
1
15
74AHC257;
74AHCT257
1I01I12I02I13I03I14I04I
S
OE
1Y 2Y 3Y 4Y
12974
131410116532
1
MNA537
handbook, halfpage
Fig.1 Pin configuration.
1
G1
15
EN
2
3
5
6
11
10
14
13
MUX
1
1
MNA538
4
7
9
12
handbook, halfpage
1I
2
1I
3
2I
5
2I
6
3I
11
3I
10
4I
14
4I
13
Fig.2 Logic symbol.
0
1
0
1
SELECTOR
0
1
0
1
S
3-STATE
MULTIPLEXER
OUTPUTS
OE
151
1Y
2Y
3Y
4Y
MNA540
4
7
9
12
Fig.3 IEC logic symbol.
2000 Apr 03 4
Fig.4 Functional diagram.
Philips Semiconductors Product specification
Quad 2-input multiplexer; 3-state
handbook, full pagewidth
1I
0
1I
1
2I
0
2I
1
3I
0
3I
1
4I
0
4I
1
74AHC257;
74AHCT257
1Y
2Y
3Y
4Y
OE
MNA539
S
Fig.5 Logic diagram.
2000 Apr 03 5
Philips Semiconductors Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient temperature see DC and AC
characteristics per
device
t
r,tf
(∆t/∆V)
input rise and fall time ratios VCC= 3.3 ±0.3 V −−100 −−−ns/V
=5±0.5 V −−20 −−20 ns/V
V
CC
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output clamping diode
VO< −0.5 V or VO>VCC+ 0.5 V; note 1 −±20 mA
current
I
O
I
CC;IGND
T
stg
P
D
DC output sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range: −40 to +125 °C; note 2 − 500 mW
74AHC 74AHCT
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of P
derates linearly with 8 mW/K.
D
For TSSOP packages: above 60 °C the value of PDderates linearly with 5.5 mW/K.
2000 Apr 03 6