Philips 74AHC541PW, 74AHCT541PW, 74AHCT541DB, 74AHCT541D, 74AHC541DB Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

74AHC541; 74AHCT541

Octal buffer/line driver; 3-state

Product specification

1999 Nov 24

Supersedes data of 1998 Sep 21

File under Integrated Circuits, IC06

Philips Semiconductors

Product specification

 

 

Octal buffer/line driver; 3-state

74AHC541; 74AHCT541

 

 

 

 

FEATURES

·ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

·Balanced propagation delays

·All inputs have a Schmitt-trigger action

·Inputs accepts voltages higher than VCC

·For AHC only: operates with CMOS input levels

·For AHCT only: operates with TTL input levels

·Specified from -40 to +85 °C and -40 to +125 °C.

QUICK REFERENCE DATA

Ground = 0 V; Tamb = 25 °C; tr = tf £ 3.0 ns.

DESCRIPTION

The 74AHC/AHCT541 is a high-speed Si-gate CMOS device.

The 74AHC/AHCT541 are octal non-inverting buffer/line drivers with 3-state bus compatible outputs.

The 3-state outputs are controlled by the output enable inputs OE0 and OE1.

A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

 

 

AHC

AHCT

 

 

 

 

 

 

 

 

 

 

tPHL/tPLH

propagation delay An to Yn

CL = 15 pF; VCC = 5 V

3.5

3.5

ns

CI

input capacitance

VI = VCC or GND

3

3

pF

CO

output capacitance

 

4.0

4.0

pF

CPD

power dissipation capacitance

CL = 50 pF; f = 1 MHz;

10

12

pF

 

 

notes 1 and 2

 

 

 

 

 

 

 

 

 

Notes

1.CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz; fo = output frequency in MHz;

å (CL ´ VCC2 ´ fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

1999 Nov 24

2

Philips Semiconductors

 

 

 

 

 

Product specification

 

 

 

 

 

 

 

 

 

Octal buffer/line driver; 3-state

 

74AHC541; 74AHCT541

 

 

 

 

 

 

 

 

 

FUNCTION TABLE

 

 

 

 

 

 

See note 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

0

 

 

1

An

 

Yn

OE

OE

 

L

 

L

L

 

L

 

 

 

 

 

 

 

 

L

 

L

H

 

H

 

 

 

 

 

 

 

 

X

 

H

X

 

Z

 

 

 

 

 

 

 

 

H

 

X

X

 

Z

 

 

 

 

 

 

 

 

 

Note

1.H = HIGH voltage level; L = LOW voltage level; X = don’t care;

Z = high-impedance OFF-state.

ORDERING INFORMATION

OUTSIDE NORTH

NORTH AMERICA

 

PACKAGES

 

 

 

 

 

AMERICA

PINS

PACKAGE

MATERIAL

CODE

 

 

 

 

 

 

 

 

 

74AHC541D

74AHC541D

20

SO

plastic

SOT163-1

 

 

 

 

 

 

74AHC541PW

74AHC541PW DH

20

TSSOP

plastic

SOT360-1

 

 

 

 

 

 

74AHCT541D

74AHCT541D

20

SO

plastic

SOT163-1

 

 

 

 

 

 

74AHCT541PW

7AHCT541PW DH

20

TSSOP

plastic

SOT360-1

 

 

 

 

 

 

PINNING

PIN

 

 

 

SYMBOL

DESCRIPTION

 

 

 

 

 

 

1

 

 

 

0

output enable input

OE

2, 3, 4, 5, 6, 7, 8 and 9

 

A0 to A7

data inputs

10

 

GND

ground (0 V)

 

 

 

 

11, 12, 13, 14, 15, 16, 17 and 18

 

Y7 to Y0

data inputs/outputs

19

 

 

1

output enable input

OE

20

 

VCC

DC supply voltage

1999 Nov 24

3

Philips 74AHC541PW, 74AHCT541PW, 74AHCT541DB, 74AHCT541D, 74AHC541DB Datasheet

Philips Semiconductors

Product specification

 

 

Octal buffer/line driver; 3-state

74AHC541; 74AHCT541

 

 

 

 

 

 

 

 

VCC

OE0

1

 

20

 

 

 

 

 

 

 

 

 

 

A0

2

 

19

OE1

 

A1

 

 

 

Y0

 

3

 

18

 

 

 

 

 

 

Y1

 

A2

4

 

17

 

A3

 

 

 

Y2

 

5

541

16

 

A4

 

 

Y3

 

6

 

15

 

A5

 

 

 

Y4

 

7

 

14

 

A6

8

 

 

Y5

 

 

13

 

A7

9

 

 

Y6

 

 

12

GND 10

 

 

Y7

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

MNA178

 

 

 

Fig.1 Pin configuration.

handbook, halfpage

 

A0

 

 

 

Y0

18

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

A1

 

 

 

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

handbook, halfpage

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

&

EN

 

 

 

 

A2

 

 

 

 

Y2

 

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

 

Y3

 

 

 

2

 

 

 

 

 

 

18

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

15

 

 

3

 

 

 

 

 

 

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

 

Y4

 

 

 

4

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

14

 

 

5

 

 

 

 

 

 

15

 

 

A

 

 

 

 

 

 

 

Y

 

 

 

 

6

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

5

 

 

 

 

 

5

 

13

 

 

7

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

Y6

12

 

9

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

A7

 

 

 

 

Y7

11

 

 

 

 

 

 

MNA180

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

OE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

OE1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MNA179

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fig.2 Logic symbol.

Fig.3 IEEE/IEC logic symbol.

1999 Nov 24

4

Philips Semiconductors

 

 

 

 

 

 

Product specification

 

 

 

 

 

 

 

 

 

 

Octal buffer/line driver; 3-state

 

74AHC541; 74AHCT541

 

 

 

 

 

 

 

 

 

 

 

 

 

RECOMMENDED OPERATING CONDITIONS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

 

CONDITIONS

 

74AHC

 

 

74AHCT

 

UNIT

 

 

 

 

 

 

 

 

 

 

MIN.

TYP.

MAX.

MIN.

 

TYP.

 

MAX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

DC supply voltage

 

 

2.0

5.0

5.5

4.5

 

5.0

 

5.5

V

VI

input voltage

 

 

0

5.5

0

 

 

5.5

V

VO

output voltage

 

 

0

VCC

0

 

 

VCC

V

Tamb

operating ambient temperature

 

see DC and AC

40

+25

+85

40

 

+25

 

+85

°C

 

 

 

characteristics per

40

+25

+125

40

 

+25

 

+125

°C

 

 

 

device

 

 

 

 

 

 

 

 

 

tr,tf ( t/ f)

input rise and fall times

 

VCC = 3.3 ±0.3 V

100

 

 

ns/V

 

 

 

VCC = 5 ±0.5 V

20

 

 

20

 

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

 

 

 

 

 

 

VCC

DC supply voltage

 

0.5

+7.0

V

VI

input voltage

 

0.5

+7.0

V

IIK

DC input diode current

VI < −0.5 V; note 1

20

mA

IOK

DC output diode current

VO < −0.5 V or VO > VCC + 0.5 V; note 1

±20

mA

IO

DC output source or sink current

0.5 V < VO < VCC + 0.5 V

±25

mA

ICC

DC VCC or GND current

 

±75

mA

Tstg

storage temperature

 

65

+150

°C

PD

power dissipation per package

for temperature range: 40 to +125 °C; note 2

500

mW

Notes

1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2.For SO-package: above 70 °C the value of PD derates linearly with 8 mW/K.

For TSSOP-package: above 60 °C the value of PD derates linearly with 5.5 mW/K.

1999 Nov 24

5

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