Philips 74AHCT30, 74AHC30 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC30; 74AHCT30
8-input NAND gate
Product specification
File under Integrated Circuits, IC06
1999 Nov 30
Philips Semiconductors Product specification
8-input NAND gate 74AHC30; 74AHCT30
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• Inputs accept voltages higher than V
CC
DESCRIPTION
The 74AHC/AHCT30 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT30 provide the 8-input NAND function.
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Output capability: standard
• ICC category: SSI
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
propagation delay
CL= 15 pF; VCC= 5 V 3.6 3.3 ns
A, B, C, D, E, F, G, H to Y
C
I
C
O
C
PD
input capacitance 3.0 3.0 pF
output capacitance 4.0 4.0 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz;
notes 1 and 2
TYPICAL
UNIT
AHC AHCT
10 12 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
2
P
D=CPD
× V
× fi+ ∑ (CL× V
CC
fi= input frequency in MHz;
fo= output frequency in MHz;
∑ (CL× V
2
× fo) = sum of outputs;
CC
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
2
× fo) where:
CC
1999 Nov 30 2
Philips Semiconductors Product specification
8-input NAND gate 74AHC30; 74AHCT30
FUNCTION TABLE
See note 1.
INPUTS OUTPUTS
ABCDEFGH Y
LXXXXXXX H
XLXXXXXX H
XXLXXXXX H
XXXLXXXX H
XXXXLXXX H
XXXXXLXX H
XXXXXXLX H
XXXXXXXL H
HHHHHHΗHL
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74AHC30D −40 to +125 °C 14 SO plastic SOT108-1
74AHCT30D 14 SO plastic SOT108-1
74AHC30PW 14 TSSOP plastic SOT402-1
74AHCT30PW 14 TSSOP plastic SOT402-1
PINNING
PIN SYMBOL DESCRIPTION
1 A data input
2 B data input
3 C data input
4 D data input
5 E data input
6 F data input
7 GND ground (0 V)
8 Y data output
9, 10 and 13 n.c. not connected
11 G data input
12 H data input
14 V
TEMPERATURE
RANGE
CC
PINS PACKAGE MATERIAL CODE
DC supply voltage
1999 Nov 30 3
Philips Semiconductors Product specification
8-input NAND gate 74AHC30; 74AHCT30
handbook, halfpage
A
1
B
2
3
C
4
D
E
F
GND
30
5
6
7
MNA487
Fig.1 Pin configuration.
V
14
CC
13
n.c.
12
H
11
G
10
n.c.
9
n.c.
8
Y
handbook, halfpage
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
Y
MNA488
8
Fig.2 Functional diagram.
handbook, halfpage
1
2
3
4
5
6
11
12
&
8
MNA489
Fig.3 IEC logic symbol.
1999 Nov 30 4
handbook, halfpage
A
B
C
D
E
F
G
H
Y
MNA490
Fig.4 Logic diagram.Fig.4 Logic diagram.
Philips Semiconductors Product specification
8-input NAND gate 74AHC30; 74AHCT30
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
74AHC 74AHCT
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall rates VCC= 3.3 ±0.3 V −−100 −−−ns/V
r,tf
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature
see DC and AC
characteristics per device
V
=5±0.5 V −−20 −−20
CC
−40 +25 +85 −40 +25 +85 °C
−40 +25 +125 −40 +25 +125 °C
0 − V
CC
CC
V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
DC input diode current VI< −0.5 V; note 1 −−20 mA
DC output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range from
− 500 mW
−40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO-packages: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP-packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Nov 30 5
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