Philips 74AHCT1G125, 74AHC1G125 Datasheet
INTEGRATED CIRCUITS
DATA SH EET
74AHC1G125; 74AHCT1G125
Bus buffer/line driver; 3-state
Product specification
Supersedes data of 1998 Dec 07
File under Integrated Circuits, IC06
1999 Jun 15
Philips Semiconductors Product specification
Bus buffer/line driver; 3-state 74AHC1G125; 74AHCT1G125
FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard.
DESCRIPTION
The 74AHC1G/AHCT1G125 is a
high-speed Si-gate CMOS device.
The 74AHC1G/AHCT1G125 provides
one non-inverting buffer/line driver
with 3-state output. The 3-state output
is controlled by the output enable
input (
OE). A HIGH at OE causes the
output to assume a high-impedance
OFF-state.
FUNCTION TABLE
See note 1.
INPUTS OUTPUT
OE inA outY
LL L
LH H
HX Z
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
PD
propagation delay
inA to outY
input capacitance 1.5 1.5 pF
power dissipation
capacitance
CL= 15 pF;
VCC=5V
CL= 50 pF;
f = 1 MHz;
notes 1 and 2
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
a) PD=CPD× V
2
× fi+(CL×V
CC
2
× fo) where:
CC
b) fi= input frequency in MHz;
c) fo= output frequency in MHz;
d) CL= output load capacitance in pF;
e) VCC= supply voltage in V.
2. The condition is VI= GND to VCC.
PINNING
PIN SYMBOL DESCRIPTION
1 OE output enable input
2 inA data input
3 GND ground (0 V)
4 outY data output
5V
CC
DC supply voltage
TYPICAL
UNIT
AHC1G AHCT1G
3.4 3.4 ns
911 pF
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF state.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE MARKING
74AHC1G125GW −40 to +85 °C 5 SC-88A plastic SOT353 AM
74AHCT1G125GW 5 SC-88A plastic SOT353 CM
1999 Jun 15 2
Philips Semiconductors Product specification
Bus buffer/line driver; 3-state 74AHC1G125; 74AHCT1G125
handbook, halfpage
OE
inA
GND
1
2
125
3
MNA117
V
5
outY
4
Fig.1 Pin configuration.
CC
handbook, halfpage
inA outY
2
1
OE
MNA118
Fig.2 Logic symbol.
4
handbook, halfpage
2
1
OE
MNA119
4
Fig.3 IEC logic symbol.
1999 Jun 15 3
handbook, halfpage
inA
OE
Fig.4 Logic diagram.
outY
MNA120
Philips Semiconductors Product specification
Bus buffer/line driver; 3-state 74AHC1G125; 74AHCT1G125
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
74AHC1G 74AHCT1G
V
CC
V
I
V
O
T
amb
t
(∆t/∆f) input rise and fall times
r,tf
DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature range
see DC and AC
characteristics per device
−40 +25 +85 −40 +25 +85 °C
0 − V
CC
CC
VCC= 3.3 V ±0.3 V −−100 −−−ns/V
except for Schmitt-trigger
inputs
V
=5V±0.5 V −−20 −−20
CC
V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
DC supply voltage −0.5 +7.0 V
input voltage range −0.5 +7.0 V
DC input diode current VI< −0.5 −−20 mA
DC output diode current VO< −0.5 or VO>VCC+ 0.5 V; note 1 −±20 mA
DC output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
DC VCC or GND current −±75 mA
storage temperature range −65 +150 °C
power dissipation per package temperature range: −40 to +85 °C; note 2 − 200 mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of P
derates linearly with 2.5 mW/K.
D
1999 Jun 15 4
Philips Semiconductors Product specification
Bus buffer/line driver; 3-state 74AHC1G125; 74AHCT1G125
DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
V
OH
LOW-level input voltage 2.0 −− 0.5 − 0.5 V
HIGH-level output
voltage; all outputs
HIGH-level output
voltage
V
OL
LOW-level output
voltage; all outputs
LOW-level output
voltage
I
OZ
3-state OFF-state
current
I
I
I
CC
input leakage current VI=VCCor GND 5.5 −− 0.1 − 1.0 µA
quiescent supply
current
C
I
input capacitance − 1.5 10 − 10 pF
TEST CONDITIONS T
25 −40 to +85
amb
(°C)
UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX.
2.0 1.5 −−1.5 − V
3.0 2.1 −−2.1 −
5.5 3.85 −−3.85 −
3.0 −− 0.9 − 0.9
5.5 −− 1.65 − 1.65
VI=VIHor VIL;
IO= −50 µA
2.0 1.9 2.0 − 1.9 − V
3.0 2.9 3.0 − 2.9 −
4.5 4.4 4.5 − 4.4 −
V
I=VIH
or VIL;
3.0 2.58 −−2.48 − V
IO= −4.0 mA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 −
IO= −8.0 mA
VI=VIHor VIL;
IO=50µA
2.0 − 0 0.1 − 0.1 V
3.0 − 0 0.1 − 0.1
4.5 − 0 0.1 − 0.1
V
I=VIH
or VIL;
3.0 −− 0.36 − 0.44 V
IO= 4.0 mA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44
IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.25 − 2.5 µA
VI=VCCor GND;
5.5 −− 1.0 − 10 µA
IO=0
1999 Jun 15 5
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