Philips 74AHC1G08, 74AHCT1G08 DATA SHEET
INTEGRATED CIRCUITS
DATA SH EET
74AHC1G08; 74AHCT1G08
2-input AND gate
Product specification
Supersedes data of 2002 Feb 21
2002 Jun 06
Philips Semiconductors Product specification
2-input AND gate 74AHC1G08; 74AHCT1G08
FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
DESCRIPTION
The74AHC1G/AHCT1G08isahigh-speedSi-gateCMOS
device.
The 74AHC1G/AHCT1G08 provides the 2-input AND
function.
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
PD
propagation delay A and B to Y CL= 15 pF; VCC= 5 V 3.2 3.6 ns
input capacitance 1.5 1.5 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz;
notes 1 and 2
TYPICAL
UNIT
AHC1G AHCT1G
17 19 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+(CL×V
CC
CC
fi= input frequency in MHz;
= output frequency in MHz;
f
o
CL= output load capacitance in pF;
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
2
× fo) where:
2002 Jun 06 2
Philips Semiconductors Product specification
2-input AND gate 74AHC1G08; 74AHCT1G08
FUNCTION TABLE
See note 1.
INPUTS OUTPUT
AB Y
LL L
LH L
HL L
HH H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74AHC1G08GW −40 to +125 °C 5 SC-88A plastic SOT353 AE
74AHCT1G08GW −40 to +125 °C 5 SC-88A plastic SOT353 CE
74AHC1G08GV −40 to +125 °C 5 SC-74A plastic SOT753 A08
74AHCT1G08GV −40 to +125 °C 5 SC-74A plastic SOT753 C08
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE MARKING
PINNING
handbook, halfpage
PIN SYMBOL DESCRIPTION
1 B data input B
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5V
GND
CC
B
1
A
2
3
5
08
4
MNA112
Fig.1 Pin configuration.
V
CC
Y
supply voltage
handbook, halfpage
1
B
2
A
Fig.2 Logic symbol.
Y
MNA113
4
2002 Jun 06 3
Philips Semiconductors Product specification
2-input AND gate 74AHC1G08; 74AHCT1G08
handbook, halfpage
1
2
&
4
MNA114
Fig.3 IEC logic symbol.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
V
CC
V
I
V
O
T
amb
supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
ambient temperature see DC and AC
characteristics per
device
t
(∆t/∆f) input rise and fall
r,tf
times
VCC= 3.3 ±0.3 V −−100 −−−ns/V
V
=5±0.5 V −−20 −−20 ns/V
CC
handbook, halfpage
A
Y
B
MNA221
Fig.4 Logic diagram.
74AHC1G 74AHCT1G
MIN. TYP. MAX. MIN. TYP. MAX.
0 − V
CC
CC
V
−40 +25 +125 −40 +25 +125 °C
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
input diode current VI< −0.5 V −−20 mA
output diode current VO< −0.5 Vor VO>VCC+ 0.5 V; note 1 −±20 mA
output source or sink current −0.5 V < VO<VCC+ 0.5 V −±25 mA
VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range from −40 to +125 °C − 250 mW
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 Jun 06 4
Philips Semiconductors Product specification
2-input AND gate 74AHC1G08; 74AHCT1G08
DC CHARACTERISTICS
Family 74AHC1G
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER
V
IH
HIGH-level input
voltage
V
IL
LOW-level input
voltage
V
OH
HIGH-leveloutput
voltage
V
OL
LOW-level output
voltage
I
LI
input leakage
current
I
CC
quiescent supply
current
C
I
input capacitance − 1.5 10 − 10 − 10 pF
TEST CONDITIONS T
OTHER
V
CC
(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
25 −40 to +85 −40 to +125
amb
(°C)
UNIT
2.0 1.5 −−1.5 − 1.5 − V
3.0 2.1 −−2.1 − 2.1 − V
5.5 3.85 −−3.85 − 3.85 − V
2.0 −− 0.5 − 0.5 − 0.5 V
3.0 −− 0.9 − 0.9 − 0.9 V
5.5 −− 1.65 − 1.65 − 1.65 V
VI=VIHor VIL;
2.0 1.9 2.0 − 1.9 − 1.9 − V
IO= −50 µA
V
I=VIH
or VIL;
3.0 2.9 3.0 − 2.9 − 2.9 − V
IO= −50 µA
V
I=VIH
or VIL;
4.5 4.4 4.5 − 4.4 − 4.4 − V
IO= −50 µA
V
I=VIH
or VIL;
3.0 2.58 −−2.48 − 2.40 − V
IO= −4.0 mA
V
I=VIH
or VIL;
4.5 3.94 −−3.8 − 3.70 − V
IO= −8.0 mA
VI=VIHor VIL;
2.0 − 0 0.1 − 0.1 − 0.1 V
IO=50µA
V
I=VIH
or VIL;
3.0 − 0 0.1 − 0.1 − 0.1 V
IO=50µA
V
I=VIH
or VIL;
4.5 − 0 0.1 − 0.1 − 0.1 V
IO=50µA
V
I=VIH
or VIL;
3.0 −− 0.36 − 0.44 − 0.55 V
IO= 4.0 mA
V
I=VIH
or VIL;
4.5 −− 0.36 − 0.44 − 0.55 V
IO= 8.0 mA
VI=VCCor GND 5.5 −− 0.1 − 1.0 − 2.0 µA
VI=VCCor GND;
5.5 −− 1.0 − 10 − 40 µA
IO=0
2002 Jun 06 5
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