Philips 74AHC1G00, 74AHCT1G00 Technical data
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INTEGRATED CIRCUITS
DATA SH EET
74AHC1G00; 74AHCT1G00
2-input NAND gate
Product specification
Supersedes data of 2002 Feb 27
2002 May 27
Philips Semiconductors Product specification
2-input NAND gate 74AHC1G00; 74AHCT1G00
FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
DESCRIPTION
The74AHC1G/AHCT1G00isahigh-speedSi-gateCMOS
device.
The 74AHC1G/AHCT1G00 provides the 2-input NAND
function.
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
• Output capability: standard
• Specified from −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf≤3.0 ns.
amb
SYMBOL PARAMETER CONDITIONS
t
PHL/tPLH
C
I
C
PD
propagation delay A and B to Y CL= 15 pF; VCC= 5 V 3.5 3.6 ns
input capacitance 1.5 1.5 pF
power dissipation capacitance CL= 50 pF; f = 1 MHz;
notes 1 and 2
TYPICAL
UNIT
AHC1G AHCT1G
17 18 pF
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW).
PD
PD=CPD× V
2
× fi+(CL×V
CC
CC
fi= input frequency in MHz;
= output frequency in MHz;
f
o
CL= output load capacitance in pF
VCC= supply voltage in Volts.
2. The condition is VI= GND to VCC.
2
× fo) where:
2002 May 27 2
Philips Semiconductors Product specification
2-input NAND gate 74AHC1G00; 74AHCT1G00
FUNCTION TABLE
See note 1.
INPUTS OUTPUT
ABY
LLH
LHH
HLH
HHL
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74AHC1G00GW −40to +125 °C 5 SC-88A plastic SOT353 AA
74AHCT1G00GW −40 to +125 °C 5 SC-88A plastic SOT353 CA
74AHC1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 A00
74AHCT1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 C00
TEMPERATURE
RANGE
PINS PACKAGE MATERIAL CODE MARKING
PINNING
PIN SYMBOL DESCRIPTION
1 B data input B
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5V
CC
supply voltage
2002 May 27 3
Philips Semiconductors Product specification
2-input NAND gate 74AHC1G00; 74AHCT1G00
handbook, halfpage
B
GND
1
A
2
3
5
00
4
MNA096
Fig.1 Pin configuration.
V
CC
Y
handbook, halfpage
1
B
2
A
MNA097
4
Y
Fig.2 Logic symbol.
handbook, halfpage
1
2
&
4
MNA098
Fig.3 IEC logic symbol.
2002 May 27 4
handbook, halfpage
B
A
Fig.4 Logic diagram.
Y
MNA099
Philips Semiconductors Product specification
2-input NAND gate 74AHC1G00; 74AHCT1G00
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
74AHC1G 74AHCT1G
V
CC
V
I
V
O
T
amb
t
r,tf
(∆t/∆f)
supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 − 5.5 0 − 5.5 V
output voltage 0 − V
operating ambient
temperature
input rise and fall
times
see DC and AC
−40 +25 +125 −40 +25 +125 °C
characteristics per device
VCC= 3.3 ±0.3 V −−100 −−−ns/V
V
=5±0.5 V −−20 −−20 ns/V
CC
0 − V
CC
CC
V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
input diode current VI< −0.5 V −−20 mA
output diode current VO< −0.5 V or VO>VCC+ 0.5 V; note 1 −±20 mA
output source or sink current −0.5V<VO<VCC+ 0.5 V −±25 mA
VCC or GND current −±75 mA
storage temperature −65 +150 °C
power dissipation per package for temperature range from −40 to +125 °C − 250 mW
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2002 May 27 5
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