Philips 74ABTH16899DGG, 74ABTH16899DL, 74ABT16899DL, 74ABT16899DGG Datasheet

INTEGRATED CIRCUITS

74ABT16899

74ABTH16899

18-bit latched transceiver with 16-bit parity generator/checker (3-State)

Product specification

1998 Feb 25

Supersedes data of 1997 Mar 28

IC23 Data Handbook

m n r

Philips Semiconductors	Product specification
18-bit latched transceiver with 16-bit	74ABT16899
parity generator/checker (3-State)	74ABTH16899

FEATURES

•Symmetrical (A and B bus functions are identical)

•Selectable generate parity or ºfeed-throughº parity for A-to-B and

B-to-A directions

•Independent transparent latches for A-to-B and B-to-A directions

•Selectable ODD/EVEN parity

•Continuously checks parity of both A bus and B bus latches as ERRA and ERRB

•Open-collector ERR output

•Ability to simultaneously generate and check parity

•Can simultaneously read/latch A and B bus data

•Output capability: +64 mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

•Power up 3-State

•Power-up reset

•Live insertion/extraction permitted

•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

DESCRIPTION

The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input.

Parity error checking of the A and B bus latches is continuously

provided with ERRA and ERRB, even with both buses in 3-State.

The 74ABT/H16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.

FUNCTIONAL DESCRIPTION

The 74ABT/H16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions.

Transparent latch, Generate parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL) is Low, the parity generated from

A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB. (Fault detection on both input and output buses.)

Transparent latch, Feed-through parity, Check A and B bus parity:

Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU.

Latched input, Generate/Feed-through parity, Check A (and B) bus parity:

Independent latch enables (LEA and LEB) allow other permutations of:

•Transparent latch / 1 bus latched / both buses latched

•Feed-through parity / generate parity

•Check in bus parity / check out bus parity / check in and out bus parity

QUICK REFERENCE DATA

	SYMBOL			PARAMETER	CONDITIONS	TYPICAL	UNIT
					Tamb = 25°C; GND = 0V
	tPLH	Propagation delay			CL = 50pF; VCC = 5V	2.7	ns
	tPHL	An to Bn or Bn to An
	tPLH	Propagation delay			CL = 50pF; VCC = 5V	5.0	ns
	tPHL	An to ERRA
	CIN	Input capacitance			VI = 0V or VCC	4	pF
	CI/O	Output capacitance			Outputs disabled; VO = 0V or VCC	7	pF
	ICCZ	Quiescent supply current			Outputs disabled; VCC =5.5V	500	μA
	ICCL				Output Low; VCC = 5.5V	10.5	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16899 DL	BT16899 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16899 DGG	BT16899 DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16899 DL	BH16899 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16899 DGG	BH16899 DGG	SOT364-1

1998 Feb 25

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853-1960 19018

Philips Semiconductors	Product specification
18-bit latched transceiver with 16-bit	74ABT16899
parity generator/checker (3-State)	74ABTH16899

PIN CONFIGURATION

ODD/EVEN						1		56		SEL
						2		55		LEA
		OEA
		1A0				3		54		1B0
	GND					4		53		GND
		1A1				5		52		1B1
		1A2				6		51		1B2
		1A3				7		50		1B3
		1A4				8		49		1B4
		VCC				9		48		VCC
		1A5				10		47		1B5
		1A6				11		46		1B6
		1A7				12		45		1B7
1APAR						13		44		1BPAR
	1ERRA					14		43			1ERRB
	GND					15		42		GND
	2ERRA					16		41			2ERRB
2APAR						17		40		2BPAR
		2A7				18		39		2B7
		2A6				19		38		2B6
		2A5				20		37		2B5
		VCC				21		36		VCC
		2A4				22		35		2B4
		2A3				23		34		2B3
		2A2				24		33		2B2
		2A1				25		32		2B1
	GND					26		31		GND
		2A0				27		30		2B0
		LEB				28		29
										OEB
							SH00082

PIN DESCRIPTION

SYMBOL

PIN

NAME AND FUNCTION

NUMBER

1A0 - 1A7

3, 5, 6, 7, 8, 10, 11, 12

Latched A bus 3-State inputs/outputs

2A0 - 2A7

27, 25, 24, 23, 22, 20, 19, 18

1B0 - 1B7

54, 52, 51, 50, 49, 47, 46, 45

Latched B bus 3-State inputs/outputs

2B0 - 2B7

30, 32, 33, 34, 35, 37, 38, 39

1APAR

13, 17

A bus parity 3-State input

2APAR

1BPAR

44, 40

B bus parity 3-State input

2BPAR

1

Parity select input (Low for EVEN parity)

ODD/EVEN

Output enable inputs (gate A to B,

OEA, OEB

2, 29

B to A)

56

Mode select input (Low for generate)

SEL

LEA, LEB

55, 28

Latch enable inputs (transparent High)

14, 43,

1ERRA,

1ERRB

Error signal outputs (active-Low)

2ERRA, 2ERRB

16, 41

GND

4, 15, 26, 31, 42, 53

Ground (0V)

VCC

9, 21, 36, 48

Positive supply voltage

1998 Feb 25

3

Philips Semiconductors Product specification

18-bit latched transceiver with 16-bit

74ABT16899

parity generator/checker (3-State)

74ABTH16899

LOGIC SYMBOL

3

5

6

7

8

10

11

12

13

27

25

24

23

22

20

19

18

17

1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1APAR

2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2APAR

55

LEA

55

LEA

28

LEB

28

LEB

56

SEL

1ERRA

14

56

SEL

2ERRA

16

1

1

ODD/EVEN

1ERRB

43

ODD/EVEN

2ERRB

41

2

OEA

2

OEA

29

OEB

1B7 1BPAR

29

OEB

2B1 2B2 2B3 2B4 2B5 2B6 2B7 2BPAR

1B0 1B1 1B2 1B3 1B4 1B5 1B6

2B0

54

52

51

50

49

47

46

45

44

30

32

33

34

35

37

38

39

40

SH00083

PARITY AND ERROR FUNCTION TABLE

INPUTS

OUTPUTS

xPAR

S of High

xPAR

SEL

ODD/EVEN

ERRt

ERRr*

(A or B)

Inputs

(B or A)

PARITY MODES

H

H

H

Even

H

H

H

Odd

H

L

L

Odd

H

H

L

Even

L

L

L

Mode

Feed-through/check parity

Odd

L

H

H

H

L

H

Even

H

L

L

Odd

H

H

H

Even

H

L

L

Even

L

H

H

Mode

Odd

L

L

L

L

H

H

Even

H

H

H

Odd

L

L

H

Odd

L

H

L

Even

H

L

H

Mode

Generate parity

Odd

L

H

H

L

L

H

Even

L

L

H

Odd

H

H

H

Even

L

L

L

Even

L

H

H

Mode

Odd

H

L

H

H

=

High voltage level

L

=

Low voltage level

t

= Transmit±if the data path is from A→ B then

is

ERRt

ERRA

r

= Receive±if the data path is from A→ B then

is

ERRr

ERRB

*Blocked if latch is not transparent

1998 Feb 25

4

Philips Semiconductors	Product specification
18-bit latched transceiver with 16-bit	74ABT16899
parity generator/checker (3-State)	74ABTH16899

BLOCK DIAGRAM

			OE	OEB
	9±bit
	Transparent
	Latch		9±bit
			Output
			Buffer
LEA	LE
A0		1		B0
	Parity	mux
A1
				B1
	Generator	0
A2
				B2
A3
				B3
A4
				B4
A5
				B5
A6
				B6
A7
				B7
APAR
				BPAR
			9±bit
		Transparent
			Latch
	9±bit
	Output
	Buffer
OEA	OE		LE	LEB
	1
	mux	Parity
	0			ERRA
		Generator
SEL
				ERRB
ODD/		(1	of 2 parity blocks)
EVEN				SH00084

FUNCTION TABLE

INPUTS

OPERATING MODE

LEA

LEB

OEB

OEA

SEL

H

H

X

X

X

3-State A bus and B bus (input A & B simultaneously)

H

L

L

L

H

B → A, transparent B latch, generate parity from B0 - B7, check B bus parity

H

L

L

H

H

B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity

H

L

L

X

L

B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity

H

L

H

X

H

B → A, transparent B latch, parity feed-through, check B bus parity

H

L

H

H

H

B → A, transparent A & B latch, parity feed-through, check A & B bus parity

L

H

L

H

X

A → B, transparent A latch, generate parity from A0 - A7, check A bus parity

L

H

L

H

H

A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity

L

H

L

L

X

A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity

L

H

H

H

L

A → B, transparent A latch, parity feed-through, check A bus parity

L

H

H

H

H

A → B, transparent A & B latch, parity feed-through, check A & B bus parity

L

L

X

X

X

Output to A bus and B bus (NOT ALLOWED)

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

1998 Feb 25

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