Philips 74ABTH16823ADL, 74ABTH16823ADGG, 74ABT16823ADGG, 74ABT16823ADL Datasheet

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74ABT16823A

74ABTH16823A

18-bit bus interface D-type flip-flop with reset and enable (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Sep 28

IC23 Data Handbook

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Philips Semiconductors	Product specification


18-bit bus-interface D-type flip-flop	74ABT16823A
with reset and enable (3-State)	74ABTH16823A

FEATURES

•Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

•Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors

•Live insertion/extraction permitted

•Power-up 3-State

•74ABTH16823A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Power-up Reset

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION

The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT16823A has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.

Two options are available, 74ABT16823A which does not have the bus-hold feature and 74ABTH16823A which incorporates the bus-hold feature.

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
SYMBOL	PARAMETER	Tamb = 25°C; GND = 0V	TYPICAL	UNIT
		Tamb = 25°C; GND = 0V
tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.3	ns
tPHL	nCP to nQx	CL = 50pF; VCC = 5V	1.9	ns
tPHL	nCP to nQx		1.9
CIN	Input capacitance	VI = 0V or VCC	4	pF
COUT	Output capacitance	VO = 0V or VCC; 3-State	6	pF
ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
ICCL	Quiescent supply current	Outputs low; VCC = 5.5V	9	mA
ICCL		Outputs low; VCC = 5.5V	9	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER

56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16823A DL	BT16823A DL	SOT371-1

56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16823A DGG	BT16823A DGG	SOT364-1

56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16823A DL	BH16823A DL	SOT371-1

56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16823A DGG	BH16823A DGG	SOT364-1

PIN DESCRIPTION

PIN NUMBER	SYMBOL					FUNCTION

2, 27						Output enable input (active-Low)
			1OE,		2OE
54, 52, 51, 49, 48, 47, 45, 44, 43	1D0-1D8					Data inputs
42, 41, 40, 38, 37, 36, 34, 33, 31	2D0-2D8


3, 5, 6, 8, 9, 10, 12, 13, 14	1Q0-1Q8					Data outputs
15, 16, 17, 19, 20, 21, 23, 24, 26	2Q0-2Q8

56, 29	1CP, 2CP					Clock pulse input (active rising edge)

55, 30						Clock enable input (active-Low)
				1CE,	2CE
1, 28						Master reset input (active-Low)
		1MR,			2MR
4, 11, 18, 25, 32, 39, 46, 53				GND		Ground (0V)

7, 22, 35, 50				VCC		Positive supply voltage
1998 Feb 27	2					853-1791 19025

Philips Semiconductors Product specification

18-bit bus-interface D-type flip-flop									74ABT16823A
with reset and enable (3-State)								74ABTH16823A

PIN CONFIGURATION				LOGIC SYMBOL (IEEE/IEC)
	1	56	1CP
1MR	1	56	1CP		2
				1OE	2	EN1
				1OE		EN1
1OE	2	55	1CE		1
1OE	2	55	1CE	1MR	1	R2
				1MR		R2
1Q0	3	54	1D0		55
1Q0	3	54	1D0	1CE	55	G3
				1CE		G3
GND	4	53	GND	1CP	56		3C4
				1CP			3C4
1Q1	5	52	1D1		27
1Q1	5	52	1D1	2OE	27	EN5
				2OE		EN5
1Q2	6	51	1D2		28	R6
1Q2	6	51	1D2	2MR	28	R6
VCC	7	50	VCC		30	G7
				2CE	30
				2CE
1Q3	8	49	1D3	2CP	29		7C8
1Q3	8	49	1D3	2CP			7C8
1Q4	9	48	1D4		54					3	1Q0
1Q4	9	48	1D4
1Q5	10	47	1D5	1D0		4D		1, 2
				1D0	52	4D		1, 2		5
				1D1							1Q1


GND	11	46	GND		51					6
				1D2							1Q2


1Q6	12	45	1D6		49					8
				1D3							1Q3


1Q7	13	44	1D7		48					9
				1D4							1Q4


1Q8	14	43	1D8		47					10
				1D5							1Q5


2Q0	15	42	2D0		45					12
				1D6							1Q6


2Q1	16	41	2D1		44					13
				1D7							1Q7


2Q2	17	40	2D2		43					14
				1D8							1Q8


GND	18	39	GND		42					15
				2D0							2Q0


2Q3	19	38	2D3		41					16

				2D1		8D		5, 6			2Q1

2Q4	20	37	2D4		40					17
				2D2							2Q2


2Q5	21	36	2D5		38					19
				2D3							2Q3


VCC	22	35	VCC		37					20
				2D4							2Q4

2Q6	23	34	2D6		36					21
				2D5							2Q5


2Q7	24	33	2D7		34					23
				2D6							2Q6


GND	25	32	GND		33					24
				2D7							2Q7

2Q8	26	31	2D8		31					25
				2D8							2Q8

	27	30

2OE			2CE							SH00015
	28	29	2CP							SH00015
2MR	28	29	2CP
		SH00014

1998 Feb 27

Philips 74ABTH16823ADL, 74ABTH16823ADGG, 74ABT16823ADGG, 74ABT16823ADL Datasheet

Philips Semiconductors	Product specification

18-bit bus-interface D-type flip-flop	74ABT16823A
with reset and enable (3-State)	74ABTH16823A

LOGIC DIAGRAM

nCE
nD0	nD1	nD2	nD3		nD4	nD5		nD6	nD7	nD8
nCP
	CP	CP	CP	CP	CP		CP	CP	CP		CP
	nD	nD	nD	nD	nD		nD	nD	nD		nD
	R Q	R Q	R Q	R Q	R Q		R Q	R Q	R Q		R Q
nMR
nOE
n = 1 or 2	nQ0	nQ1	nQ2	nQ3		nQ4	nQ5		nQ6	nQ7	nQ8
n = 1 or 2
											SH00016

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

nCP

nDx

nQ0 ± nQ8

nOE

nMR

nCE

Clear

↑

Load and read data

↑

Hold

High impedance

High voltage level

High voltage level one set-up time prior to the Low-to-High clock transition

Low voltage level

Low voltage level one set-up time prior to the Low-to-High clock transition

NC=

No change

Don't care

High impedance ªoffº state

↑= Low to High clock transition

↑= Not a Low-to-High clock transition

1998 Feb 27

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