Philips 74ABTH16823ADL, 74ABTH16823ADGG, 74ABT16823ADGG, 74ABT16823ADL Datasheet

INTEGRATED CIRCUITS

74ABT16823A
74ABTH16823A

18-bit bus interface D-type flip-flop
with reset and enable (3-State)

Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent su ly current

18-bit bus-interface D-type flip-flop
with reset and enable (3-State)

FEA TURES

•Two sets of high speed parallel registers with positive

edge-triggered D-type flip-flops

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Live insertion/extraction permitted

•Power-up 3-State

•74ABTH16823A incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Power-up Reset

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

I

CCL

IN

Propagation delay
nCP to nQx

Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 6 pF

pp

74ABT16823A

74ABTH16823A

DESCRIPTION

The 74ABT16823A 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.

The 74ABT16823A has two 9-bit wide buffered registers with Clock
Enable (nCE
interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.

Two options are available, 74ABT16823A which does not have the
bus-hold feature and 74ABTH16823A which incorporates the
bus-hold feature.

T

amb

CL = 50pF; VCC = 5V

Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 9 mA

) and Master Reset (nMR) which are ideal for parity bus

CONDITIONS
= 25°C; GND = 0V

CC

TYPICAL UNIT

2.3

1.9
4 pF

ns

ORDERING INFORMATION

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16823A DL BT16823A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16823A DGG BT16823A DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16823A DL BH16823A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16823A DGG BH16823A DGG SOT364-1

PIN DESCRIPTION

54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31

3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

1998 Feb 27 853-1791 19025

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

PIN NUMBER SYMBOL FUNCTION

2, 27 1OE, 2OE Output enable input (active-Low)

1D0-1D8
2D0-2D8

1Q0-1Q8

2Q0-2Q8
56, 29 1CP, 2CP Clock pulse input (active rising edge)
55, 30 1CE, 2CE Clock enable input (active-Low)

1, 28 1MR, 2MR Master reset input (active-Low)

7, 22, 35, 50 V

CC

2

Data inputs

Data outputs

Positive supply voltage

Philips Semiconductors Product specification

18-bit bus-interface D-type flip-flop
with reset and enable (3-State)

PIN CONFIGURATION

1
2

1OE

3

1Q0

4

GND

5

1Q1

6

1Q2

7

V

CC

8

1Q3

9

1Q4

10

1Q5

GND

11

1Q6

12

1Q7

13

1Q8

14

2Q0

15

2Q1

16

2Q2

17

GND

18

2Q3

19

2Q4

20

2Q5

21

V

22

CC

23

2Q6

24

2Q7

25

GND

26

2Q8

27

2OE

28 29

2MR

561MR

1CP

55

1CE

54

1D0
GND

53

1D1

52

1D2

51

V

50

CC

1D3

49

1D4

48

1D5

47

GND

46

1D6

45

1D7

44

1D8

43

2D0

42

2D1

41

2D2

40

GND

39

2D3

38

2D4

37

2D5

36

V

35

CC

34

2D6

33

2D7

32

GND

31

2D8

30

2CE
2CP

LOGIC SYMBOL (IEEE/IEC)

1OE
1MR

1CE

1CP
2OE
2MR

2CE

2CP

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2

1
55
56
27
28
30
29

54
52
51
49
48
47
45
44
43
42

41
40
38
37
36
34
33
31

EN1
R2
G3

3C4
EN5
R6
G7

7C8

4D

8D

74ABT16823A

74ABTH16823A

1, 2 ∇

5, 6 ∇

3
5
6
8

9
10
12
13
14
15
16
17
19
20
21
23
24
25

SH00015

1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8

2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8

1998 Feb 27

SH00014

3

Philips Semiconductors Product specification

OPERATING MODE

Load and read data

18-bit bus-interface D-type flip-flop
with reset and enable (3-State)

LOGIC DIAGRAM

nCE

nD0

nCP

nMR

nOE

n = 1 or 2

nD1

CP CP CP CP CP CP CP CP CP

nD

R

nD

R

Q

nQ0

nD2

Q Q Q Q Q Q Q Q

nQ1

74ABT16823A

74ABTH16823A

nD3

nD

R

nD

R

nQ2

nQ3

nD4

nD5

nD

R

nD

R

nQ4

nQ5

nD6

nD7

nD

R

nQ6

nD8

nD

R

nQ7

nD

R

nQ8

SH00016

FUNCTION TABLE

INPUTS OUTPUTS

nOE nMR nCE nCP nDx nQ0 – nQ8

L L X X X L Clear
L H L ↑ h H
L H L ↑ l L
L H H ↑ X NC Hold
H X X X X Z High impedance

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

1998 Feb 27

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