Philips 74ABTH16821ADL, 74ABTH16821ADGG, 74ABT16821ADL, 74ABT16821ADGG Datasheet

INTEGRATED CIRCUITS

74ABT16821A

74ABTH16821A

20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Sep 28

IC23 Data Handbook

m n r

Philips Semiconductors	Product specification
20-bit bus-interface D-type flip-flop;	74ABT16821A
positive-edge trigger (3-State)	74ABTH16821A

FEATURES

•20-bit positive-edge triggered register

•Multiple VCC and GND pins minimize switching noise

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•74ABTH16821A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/-32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

QUICK REFERENCE DATA

DESCRIPTION

The 74ABT16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT16821A has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and

Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.

Two options are available, 74ABT16821A which does not have the bus-hold feature and 74ABTH16821A which incorporates the bus-hold feature.

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.4	ns
	tPHL	nCP to nQx		2.0
	CIN	Input capacitance	VI = 0V or VCC	3	pF
	COUT	Output capacitance	VO = 0V or VCC; 3-State	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs LOW; VCC = 5.5V	10	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16821A DL	BT16821A DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16821A DGG	BT16821A DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16821A DL	BH16821A DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16821A DGG	BH16821A DGG	SOT364-1

PIN DESCRIPTION

	PIN NUMBER	SYMBOL					FUNCTION
	55, 54, 52, 51, 49, 48, 47, 45, 44, 43,	1D0 - 1D9					Data inputs
	42, 41, 40, 38, 37, 36, 34, 33, 31, 30	2D0 - 2D9
	2, 3, 5, 6, 8, 9, 10, 12, 13, 14,	1Q0 - 1Q9					Data outputs
	15, 16, 17, 19, 20, 21, 23, 24, 26, 27	2Q0 - 2Q9
	1, 28						Output enable inputs (active-Low)
			1OE,	2OE
	56, 29	1CP, 2CP					Clock pulse inputs (active rising edge)
	4, 11, 18, 25, 32, 39, 46, 53		GND				Ground (0V)
	7, 22, 35, 50		VCC				Positive supply voltage

1998 Feb 27

2

853-1796 19026

Philips Semiconductors	Product specification
20-bit bus-interface D-type flip-flop;	74ABT16821A
positive-edge trigger (3-State)	74ABTH16821A

PIN CONFIGURATION

1OE			1		56		1CP
1Q0			2		55		1D0
1Q1			3		54		1D1
GND			4		53		GND
1Q2			5		52		1D2
1Q3			6		51		1D3
VCC			7		50		VCC
1Q4			8		49		1D4
1Q5			9		48		1D5
1Q6			10		47		1D6
GND			11		46		GND
1Q7			12		45		1D7
1Q8			13		44		1D8
1Q9			14		43		1D9
2Q0			15		42		2D0
2Q1			16		41		2D1
2Q2			17		40		2D2
GND			18		39		GND
2Q3			19		38		2D3
2Q4			20		37		2D4
2Q5			21		36		2D5
VCC			22		35		VCC
2Q6			23		34		2D6
2Q7			24		33		2D7
GND			25		32		GND
2Q8			26		31		2D8
2Q9			27		30		2D9
2OE			28		29		2CP
				SH00001

LOGIC SYMBOL

			56					54		52		51		49		48		47		45		44		43
				1D0				1D1		1D2		1D3		1D4		1D5		1D6		1D7		1D8		1D9
56				1CP
1
				1OE
				1Q0				1Q1		1Q2		1Q3		1Q4		1Q5		1Q6		1Q7		1Q8		1Q9
			2					3		5		6		8		9		10		12		13		14
			42					41		40		38		37		36		34		33		31		30
				2D0				2D1		2D2		2D3		2D4		2D5		2D6		2D7		2D8		2D9
29				2CP
28
				2OE
				2Q0				2Q1		2Q2		2Q3		2Q4		2Q5		2Q6		2Q7		2Q8		2Q9
			15					16		17		19		20		21		23		24		26		27

SH00002

LOGIC SYMBOL (IEEE/IEC)

					1
	1OE					EN2
	1CP				56		C1
					28
	2OE					EN4
	2CP				29		C3
					55				2
	1D0					1D		2		1Q0
					54				3
	1D1									1Q1
					52				5
	1D2									1Q2
					51				6
	1D3									1Q3
					49				8
	1D4									1Q4
					48				9
	1D5									1Q5
					47				10
	1D6									1Q6
					45				12
	1D7									1Q7
					44				13
	1D8									1Q8
					43				14
	1D9									1Q9
					42				15
	2D0					3D		4		2Q0
					41				16
	2D1									2Q1
					40				17
	2D2									2Q2
					38				19
	2D3									2Q3
					37				20
	2D4									2Q4
					36				21
	2D5									2Q5
					34				23
	2D6									2Q6
					33				24
	2D7									2Q7
					31				26
	2D8									2Q8
					30				27
	2D9									2Q9
									SH00003

FUNCTION TABLE

			INPUTS				INTERNAL	OUTPUTS	OPERATING
				nCP		nDx	REGISTER	nQ0 - nQ9	MODE
nOE
	L			↑		l	L	L	Load and read
	L			↑		h	H	H	register
	L			↑		X	NC	NC	Hold
	H			↑		X	NC	Z	Disable
	H			↑		Dn	Dn	Z	outputs

H = High voltage level

h= High voltage level one set-up time prior to the Low-to-High clock transition

L = Low voltage level

l= Low voltage level one set-up time prior to the Low-to-High clock transition

NC=		No change
X	=	Don't care
Z	=	High impedance ªoffº state

↑= Low to High clock transition

↑= Not a Low-to-High clock transition

1998 Feb 27

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