Philips 74abt h16821a DATASHEETS

INTEGRATED CIRCUITS

74ABT16821A
74ABTH16821A

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent supply current

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

FEA TURES

•20-bit positive-edge triggered register

•Multiple V

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•74ABTH16821A incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Output capability: +64mA/-32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

and GND pins minimize switching noise

CC

74ABT16821A

74ABTH16821A

DESCRIPTION

The 74ABT16821A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.

The 74ABT16821A has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE

Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE
independent of the register operation. When nOE
the register appears at the outputs. When nOE
are in high impedance “off” state, which means they will neither drive
nor load the bus.

Two options are available, 74ABT16821A which does not have the
bus-hold feature and 74ABTH16821A which incorporates the
bus-hold feature.

) control gates.

) controls all ten 3-State buffers

is Low, the data in

is High, the outputs

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

I

CCL

IN

Propagation delay
nCP to nQx

Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 7 pF

pp

CONDITIONS

T

= 25°C; GND = 0V

amb

CL = 50pF; VCC = 5V

CC

Outputs disabled; VCC = 5.5V 500 µA

Outputs LOW; VCC = 5.5V 10 mA

TYPICAL UNIT

2.4

2.0
3 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16821A DL BT16821A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16821A DGG BT16821A DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16821A DL BH16821A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16821A DGG BH16821A DGG SOT364-1

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

55, 54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31, 30

2, 3, 5, 6, 8, 9, 10, 12, 13, 14,

15, 16, 17, 19, 20, 21, 23, 24, 26, 27

1, 28 1OE, 2OE Output enable inputs (active-Low)

56, 29 1CP, 2CP Clock pulse inputs (active rising edge)

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

1D0 - 1D9
2D0 - 2D9

1Q0 - 1Q9
2Q0 - 2Q9

CC

Data inputs

Data outputs

Positive supply voltage

ns

1998 Feb 27 853-1796 19026

2

Philips Semiconductors Product specification

INTERNAL

OPERATING

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

PIN CONFIGURATION

GND

GND

GND

GND

LOGIC SYMBOL

56 54 52 51 49 48 47 45 44 43

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

1CP

56

1OE

1

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

2 3 5 6 8 9 10 12 13 14

42 41 40 38 37 36 34 33 31 30

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

29

2CP

28

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

1
2

1Q0

3

1Q1

4
5

1Q2

6

1Q3

7

V

CC

8

1Q4

9

1Q5

10

1Q6

11
12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

18
19

2Q3

20

2Q4

21

2Q5

22

V

CC

23

2Q6

24

2Q7

25
26

2Q8

27

2Q9

28 29

2OE

561OE
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30

SH00001

1CP
1D0
1D1
GND
1D2
1D3
V

CC

1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V

CC

2D6
2D7
GND
2D8
2D9
2CP

1D8 1D9

1Q8 1Q9

2D8 2D9

2Q8 2Q9

74ABT16821A

74ABTH16821A

LOGIC SYMBOL (IEEE/IEC)

1

1OE

56

1CP

28

2OE

29

2CP

55

1D0

54

1D1

52

1D2

51

1D3

49

1D4

48

1D5

47

1D6

45

1D7

44

1D8

43

1D9

42

2D0

41

2D1

40

2D2

38

2D3

37

2D4

36

2D5

34

2D6

33

2D7

31

2D8

30

2D9

FUNCTION TABLE

INPUTS

nOE nCP nDx

L

↑

L
L ↑ X NC NC Hold

H
H

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

l

↑

h

↑

X

Dn

↑

EN2

C1

EN4

C3

1D

3D

INTERNAL
REGISTER

L

H

NC

Dn

2 ∇

4 ∇

OUTPUTS
nQ0 - nQ9

L

H

Z
Z

2

1Q0

3

1Q1

5

1Q2

6

1Q3

8

1Q4

9

1Q5

10

1Q6

12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

19

2Q3

20

2Q4

21

2Q5

23

2Q6

24

2Q7

26

2Q8

27

2Q9

SH00003

OPERATING

MODE

Load and read

register

Disable
outputs

1998 Feb 27

15 16 17 19 20 21 23 24 26 27

SH00002

3