Philips 74ABTH16646DL, 74ABTH16646DGG, 74ABT16646DGG, 74ABT16646DL Datasheet
INTEGRATED CIRCUITS
74ABT16646
74ABTH16646
16-bit bus transceiver/register (3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors Product specification
I
Quiescent supply current
16-bit bus transceiver/register (3-State)
FEA TURES
•Independent registers for A and B buses
•Multiple VCC and GND pins minimize switching noise
•Live insertion/extraction permitted
•Power–up 3-State
•Power–up reset
•Multiplexed real-time and stored data
•Outputs sink 64mA and source 32mA
•Latch–up protection exceeds 500mA per JEDEC Std 17
•74ABTH16646 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
C
C
CCZ
IN
I/O
Propagation delay
nAx to nBx
Input capacitance VI = 0V or V
I/O capacitance VO = 0V or VCC; 3-State 7 pF
pp
74ABT16646
74ABTH16646
DESCRIPTION
The 74ABT16646 high–performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16646 16-bit transceiver/register consists of two sets of
bus transceiver circuits with 3-State outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or from the internal registers. Data on the
A or B bus will be clocked into the registers as the appropriate clock
pin goes High. Output Enable (nOE
provided to control the transceiver function. In the transceiver mode,
data present at the high impedance port may be stored in either the
A or B register or both.
The select (nSAB, nSBA) pins determine whether data is stored or
transferred through the device in real-time. The nDIR determines
which bus will receive data when the nOE
isolation mode (nOE = High), data from Bus A may be stored in the
B register and/or data from Bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
Two options are available, 74ABT16646 which does not have the
bus-hold feature and 74ABTH16646 which incorporates the
bus-hold feature.
CONDITIONS
T
= 25°C; GND = 0V
amb
CL = 50pF; VCC = 5V
CC
Outputs disabled; VCC =5.5V 550 µA
Outputs low; VCC =5.5V 9 mA
) and Direction (nDIR) pins are
is active Low. In the
TYPICAL UNIT
3.3
2.7
3 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16646 DL BT16646 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16646 DGG BT16646 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16646 DL BH16646 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16646 DGG BH16646 DGG SOT364-1
PIN DESCRIPTION
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
1998 Feb 27 853-1782 19026
PIN NUMBER SYMBOL NAME AND FUNCTION
2, 55, 27, 30 1CPAB, 1CPBA, 2CPAB, 2CPBA Clock input A to B / Clock input B to A
3, 54, 26, 31 1SAB, 1SBA, 2SAB, 2SBA Select input A to B / Select input B to A
1, 28 1DIR, 2DIR Direction control inputs
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
56, 29 1OE, 2OE Output enable inputs
7, 22, 35, 50 V
CC
2
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Positive supply voltage
Philips Semiconductors Product specification
OPERATING MODE
16-bit bus transceiver/register (3-State)
PIN CONFIGURATION
1DIR
1CPAB
1SAB
GND
1A0
1A1
V
CC
1A2
1A3
1A4
GND
1A5
1A6
1A7
2A0
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2SAB
2CPAB
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SH00026
56
1OE
55
1CPBA
1SBA
54
GND
53
1B0
52
1B1
51
50
V
CC
49
1B2
1B3
48
1B4
47
GND
46
1B5
45
1B6
44
1B7
43
2B0
42
41
2B1
2B2
40
GND
39
2B3
38
37
2B4
36
2B5
35
V
CC
34
2B6
33
2B7
32
GND
31
2SBA
30
2CPBA
29
20E
74ABT16646
74ABTH16646
FUNCTION TABLE
INPUTS DATA I/O
nOE nDIR nCPAB nCPBA nSAB nSBA nAx nBx
X X ↑ X X X Input
X
X
L
H
X
X
Unspecified
output*
Input Input
Output Input
Input Output
X X X ↑ X X
H
H
L
L
L
L
X
X
L
L
H
H
↑
H or L
X
X
X
H or L
↑
H or L
X
H or L
X
X
X
X
X
X
L
H
H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
* The data output function may be enabled or disabled by various signals at the nOE
data at the bus pins will be stored on every Low–to–High transition of the clock.
1998 Feb 27
3
Unspecified
output*
Store A, B unspecified
Input Store B, A unspecified
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
input. Data input functions are always enabled, i.e.,
Philips Semiconductors Product specification
16-bit bus transceiver/register (3-State)
LOGIC SYMBOL (IEEE/IEC)
56
1OE
1DIR
1CPBA
1SBA
1CPAB
1SAB
2OE
2DIR
2CPBA
2SBA
2CPAB
2SAB
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
1
∇1
6D
7
17
1
∇8
13D 14
114
54D
5
1
1
2∇
12 11D
12 1
1
9∇
52
1B0
51
1B1
49
1B2
48
1B3
47
1B4
45
1B5
44
1B6
43
1B7
42
2B0
41
2B1
40
2B2
38
2B3
37
2B4
36
2B5
34
2B6
33
2B7
LOGIC SYMBOL
2
3
1 1DIR
55 1CPBA
54 1SBA
56 1OE
27
26
28 2DIR
30 2CPBA
31 2SBA
29 2OE
74ABT16646
74ABTH16646
5 9 10 12 13 1468
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1CPAB
1SAB
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
52 51 49 48 47 45 44 43
15 16 17 19 20 21 23 24
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
2CPAB
2SAB
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
42 41 40 38 37 36 34 33
SH00027
1998 Feb 27
SH00025
4
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