Philips 74ABTH16543DL, 74ABTH16543DGG, 74ABT16543DL, 74ABT16543DGG Datasheet

INTEGRATED CIRCUITS

74ABT16543

74ABTH16543

16-bit latched transceivers with dual enable (3-State)

Product specification

1998 Feb 27

Supersedes data of 1995 Aug 17

IC23 Data Handbook

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Philips Semiconductors	Product specification
16-bit latched transceivers with dual enable	74ABT16543
(3-State)	74ABTH16543

FEATURES

•Two 8-bit octal transceivers with D-type latch

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Multiple VCC and GND pins minimize switching noise

•Back-to-back registers for storage

•Separate controls for data flow in each direction

•74ABTH16543 incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/±32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

•See 74ABT161543 for same function with Master Reset control pins

DESCRIPTION

The 74ABT16543 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT16543 16-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (nLEAB, nLEBA) and Output Enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA.

Two options are available, 74ABT16543 which does not have the bus-hold feature and 74ABTH16543 which incorporates the bus-hold feature.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF; VCC = 5V	2.5	ns
	tPHL	nAx to nBx		2.2
	CIN	Input capacitance	VI = 0V or VCC	3	pF
	CI/O	I/O capacitance	VO = 0V or VCC; 3-State	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	550	μA
	ICCL		Outputs low; VCC = 5.5V	9	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16543 DL	BT16543 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16543 DGG	BT16543 DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16543 DL	BH16543 DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16543 DGG	BH16543 DGG	SOT364-1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

5, 6, 8, 9, 10, 12, 13, 14

1A0 ± 1A7,

Data inputs/outputs

15, 16, 17, 19, 20, 21, 23, 24

2A0 ± 2A7

52, 51, 49, 48, 47, 45, 44, 43

1B0 ± 1B7,

Data inputs/outputs

42, 41, 40,38, 37, 36, 34, 33

2B0 ± 2B7

1, 56

1OEAB,

1OEBA,

A to B / B to A Output Enable inputs (active-Low)

28, 29

2OEAB, 2OEBA

3, 54

1EAB,

1EBA,

A to B / B to A Enable inputs (active-Low)

26, 31

2EAB, 2EBA

2, 55

1LEAB,

1LEBA,

A to B / B to A Latch Enable inputs (active-Low)

27, 30

2LEAB, 2LEBA

4, 11, 18, 25, 32, 39, 46, 53

GND

Ground (0V)

7, 22, 35, 50

VCC

Positive supply voltage

1998 Feb 27

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853-1739 19026

Philips Semiconductors Product specification

16-bit latched transceivers with dual enable		74ABT16543
(3-State)		74ABTH16543
LOGIC SYMBOL (IEEE/IEC)	PIN CONFIGURATION

1OEBA 56 1EBA 54

1LEBA 55 1OEAB 1

1EAB 3 1LEAB 2

2OEBA 29 2EBA 31

2LEBA 30 2OEAB 28

2EAB 26 2LEAB 27

1A0 5

1A1 6

1A2 8

1A3 9

1A4 10

1A5 12

1A6 13

1A7 14

2A0 15

2A1 16

2A2 17

2A3 19

2A4 20

2A5 21

2A6 23

2A7 24

					1OEAB	1	56	1OEBA
	1EN3				1LEAB	2	55	1LEBA
	G1				1EAB	3	54	1EBA
	1C5				GND	4	53	GND
	2EN4				1A0	5	52	1B0
	G2				1A1	6	51	1B1
	2C6				VCC	7	50	VCC
	7EN9				1A2	8	49	1B2
	G7				1A3	9	48	1B3
	7C11				1A4	10	47	1B4
	8EN10				GND	11	46	GND
	G8				1A5	12	45	1B5
	8C12				1A6	13	44	1B6
					1A7	14	43	1B7
	3	5D	52	1B0	2A0	15	42	2B0
	6D	4			2A1	16	41	2B1
			51	1B1	2A2	17	40	2B2
			49	1B2	GND	18	39	GND
			48	1B3	2A3	19	38	2B3
			47	1B4	2A4	20	37	2B4
			45	1B5	2A5	21	36	2B5
			44	1B6	VCC	22	35	VCC
			43
				1B7	2A6	23	34	2B6
			42
	9	11D		2B0	2A7	24	33	2B7
	12D	10			GND	25	32	GND
			41	2B1	2EAB	26	31	2EBA
			40
				2B2	2LEAB	27	30	2LEBA
			38
				2B3		28	29
					2OEAB			2OEBA
			37
				2B4
							SH00037
			36	2B5
			34	2B6
			33	2B7
			SH00036

1998 Feb 27

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Philips Semiconductors Product specification

16-bit latched transceivers with dual enable																										74ABT16543
(3-State)																								74ABTH16543
LOGIC SYMBOL														FUNCTIONAL DESCRIPTION
														The 74ABT16543 contains							two sets of eight D-type latches, with
														separate control pins for each set. Using data flow from A to B as an
																										input and the A-to-B Latch
														example, when the A-to-B Enable (nEAB)
														Enable					input are Low the A-to-B path is transparent.
																	(nLEAB)
														A subsequent Low-to-High transition of the															signal puts the A
		5		6		8	9	10	12	13	14																nLEAB
														data into the latches where it is stored and the B outputs no longer
														change with the A inputs. With								EAB	and			nOEAB		both Low, the
		1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7												3-State B output buffers are active and display the data present at
														the outputs of the A latches.
3		1EAB												Control of data flow from B to A is similar, but using the
54		1EBA								1OEAB			1																	nEBA,
2		1LEAB								1OEBA			56	nLEBA, and nOEBA inputs.
55		1LEBA
		1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
		52		51		49	48	47	45	44	43
		15		16		17	19	20	21	23	24
		2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
26		2EAB
31		2EBA								2OEAB			28
27		2LEAB								2OEBA			29
30		2LEBA
		2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
		42		41		40	38	37	36	34	33
													SH00038

FUNCTION TABLE

INPUTS

OUTPUTS

STATUS

nOEXX

nEXX

nLEXX

nAx or nBx

nBx or nAx

H

X

X

X

Z

Disabled

X

H

X

X

Z

Disabled

L

↑

L

h

Z

Disabled + Latch

L

↑

L

l

Z

L

L

↑

h

H

Latch + Display

L

L

↑

l

L

L

L

L

H

H

Transparent

L

L

L

L

L

L

L

H

X

NC

Hold

H

=

High voltage level

h

=

High voltage level one set-up time prior to the Low-to-High transition of

nLEXX

or

nEXX

(XX = AB or BA)

L

=

Low voltage level

or

(XX = AB or BA)

l

=

Low voltage level one set-up time prior to the Low-to-High transition of

nLEXX

nEXX

X

=

Don't care

↑

=

Low-to-High transition of

or

(XX = AB or BA)

nLEXX

nEXX

NC=

No change

Z

=

High impedance or ªoffº state

1998 Feb 27

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