Philips 74abt h16543 DATASHEETS
INTEGRATED CIRCUITS
74ABT16543
74ABTH16543
16-bit latched transceivers with
dual enable (3-State)
Product specification
Supersedes data of 1995 Aug 17
IC23 Data Handbook
1998 Feb 27
Philips Semiconductors Product specification
Quiescent su ly current
16-bit latched transceivers with dual enable
(3-State)
FEA TURES
•Two 8-bit octal transceivers with D-type latch
•Live insertion/extraction permitted
•Power-up 3-State
•Power-up reset
•Multiple V
and GND pins minimize switching noise
CC
•Back-to-back registers for storage
•Separate controls for data flow in each direction
•74ABTH16543 incorporates bus-hold data inputs which eliminate
the need for external pull-up resistors to hold unused inputs
•Output capability: +64mA/–32mA
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
•See 74ABT161543 for same function with Master Reset control
pins
QUICK REFERENCE DATA
SYMBOL PARAMETER
t
PLH
t
PHL
C
C
I
CCZ
I
CCL
IN
I/O
Propagation delay
nAx to nBx
Input capacitance VI = 0V or V
I/O capacitance VO = 0V or V
pp
CL = 50pF; VCC = 5V
Outputs disabled; VCC = 5.5V 550 µA
Outputs low; VCC = 5.5V 9 mA
DESCRIPTION
The 74ABT16543 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16543 16-bit registered transceiver contains two sets of
D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (nLEAB
Enable (nOEAB
permit independent control of data transfer in either direction. The
outputs are guaranteed to sink 64mA.
Two options are available, 74ABT16543 which does not have the
bus-hold feature and 74ABTH16543 which incorporates the
bus-hold feature.
CONDITIONS
T
= 25°C; GND = 0V
amb
CC
3-State 7 pF
CC;
74ABT16543
74ABTH16543
, nLEBA) and Output
, nOEBA) inputs are provided for each register to
TYPICAL UNIT
2.5
2.2
3 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16543 DL BT16543 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16543 DGG BT16543 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16543 DL BH16543 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16543 DGG BH16543 DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40,38, 37, 36, 34, 33
1, 56
28, 29
3, 54
26, 31
2, 55
27, 30
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
1A0 – 1A7,
2A0 – 2A7
1B0 – 1B7,
2B0 – 2B7
1OEAB, 1OEBA,
2OEAB, 2OEBA
1EAB, 1EBA,
2EAB, 2EBA
1LEAB, 1LEBA,
2LEAB, 2LEBA
CC
Data inputs/outputs
Data inputs/outputs
A to B / B to A Output Enable inputs (active-Low)
A to B / B to A Enable inputs (active-Low)
A to B / B to A Latch Enable inputs (active-Low)
Positive supply voltage
1998 Feb 27 853-1739 19026
2
Philips Semiconductors Product specification
16-bit latched transceivers with dual enable
(3-State)
LOGIC SYMBOL (IEEE/IEC)
1OEBA
1EBA
1LEBA
1OEAB
1EAB
1LEAB
2OEBA
2EBA
2LEBA
2OEAB
2EAB
2LEAB
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1EN3
G1
1C5
2EN4
G2
2C6
7EN9
G7
7C11
8EN10
G8
8C12
∇3
6D 4 ∇
∇911D
12D
5D
10 ∇
52
1B0
51
1B1
49
1B2
48
1B3
47
1B4
45
1B5
44
1B6
43
1B7
42
2B0
41
2B1
40
2B2
38
2B3
37
2B4
36
2B5
34
2B6
33
2B7
PIN CONFIGURA TION
1
1OEAB
2
1LEAB
1EAB
3
GND
4
1A0
5
6
1A1
7
V
CC
8
1A2
1A3
9
1A4
10
GND
11
1A5
12
1A6
13
1A7
14
2A0
15
16
2A1
2A2
17
GND
18
2A3
19
20
2A4
21
2A5
22
V
CC
23
2A6
24
2A7
GND
25
26
2EAB
27
2LEAB
28
2OEAB
74ABT16543
74ABTH16543
56
1OEBA
55
1LEBA
1EBA
54
GND
53
1B0
52
51
1B1
50
V
CC
49
1B2
1B3
48
1B4
47
GND
46
1B5
45
1B6
44
1B7
43
2B0
42
41
2B1
2B2
40
GND
39
2B3
38
37
2B4
36
2B5
35
V
CC
34
2B6
33
2B7
GND
32
31
2EBA
30
2LEBA
29
2OEBA
SH00037
1998 Feb 27
SH00036
3
Philips Semiconductors Product specification
STATUS
16-bit latched transceivers with dual enable
(3-State)
LOGIC SYMBOL
5 6 10 12 13 1489
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
3
1EAB
54
1EBA
2 1LEAB
55 1LEBA
1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7
52 51 47 45 44 4349 48
15 16 20 21 23 2417 19
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7
26
2EAB
31
2EBA
27 2LEAB
30 2LEBA
2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7
11OEAB
561OEBA
282OEAB
292OEBA
74ABT16543
74ABTH16543
FUNCTIONAL DESCRIPTION
The 74ABT16543 contains two sets of eight D-type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (nEAB
Enable (nLEAB
) input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the nLEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB
3-State B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B to A is similar, but using the nEBA
nLEBA
, and nOEBA inputs.
) input and the A-to-B Latch
and nOEAB both Low, the
,
42 41 37 36 34 3340 38
SH00038
FUNCTION TABLE
INPUTS OUTPUTS
nOEXX nEXX nLEXX nAx or nBx nBx or nAx
H X X X Z Disabled
X H X X Z Disabled
L
L
L
L
L
L
L L H X NC Hold
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High transition of nLEXX
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High transition of nLEXX
X = Don’t care
↑ = Low-to-High transition of nLEXX
NC= No change
Z = High impedance or “off” state
↑
↑
L
L
L
L
L
L
↑
↑
L
L
h
l
h
l
H
L
Z
Z
H
L
H
L
or nEXX (XX = AB or BA)
or nEXX (XX = AB or BA)
or nEXX (XX = AB or BA)
Disabled + Latch
Latch + Display
Transparent
1998 Feb 27
4
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