Philips Semiconductors Product specification
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
2
1998 Feb 27 853-1788 19027
FEA TURES
•18-bit bidirectional bus interface
•3-State buffers
•Output capability: +64mA/-32mA
•TTL input and output switching levels
•74ABTH16501A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Live insertion/extraction permitted
•Power-up reset
•Power-up 3-State
•Positive edge-triggered clock inputs
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
•Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, and latched modes.
DESCRIPTION
The 74ABT16501A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA
), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP AB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA
,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA
is active Low).
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Two options are available, 74ABT16501A which does not have the
bus-hold feature and 74ABTH16501A which incorporates the
bus-hold feature.
QUICK REFERENCE DA TA
SYMBOL PARAMETER
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL UNIT
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
CL = 50pF;
VCC = 5V
2.2
1.8
ns
C
IN
Input capacitance (Control pins) VI = 0V or V
CC
3 pF
C
I/O
I/O pin capacitance Outputs disabled; V
I/O
= 0V or V
CC
7 pF
I
CCZ