Philips 74ABTH16501ADGG, 74ABTH16501ADL, 74ABT16501ADL, 74ABT16501ADGG Datasheet

INTEGRATED CIRCUITS

74ABT16501A

74ABTH16501A

18-bit universal bus transceiver (3-State)

Product specification

1998 Feb 27

Supersedes data of 1997 Jun 12

IC23 Data Handbook

m n r

	Philips Semiconductors	Product specification
	18-bit universal bus transceiver (3-State)	74ABT16501A
		74ABTH16501A

FEATURES

•18-bit bidirectional bus interface

•3-State buffers

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•74ABTH16501A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Positive edge-triggered clock inputs

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

•Flexible operation permits 18 embedded D-type latches or flip-flops to operate in clocked, transparent, and latched modes.

DESCRIPTION

The 74ABT16501A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low).

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Two options are available, 74ABT16501A which does not have the bus-hold feature and 74ABTH16501A which incorporates the bus-hold feature.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF;	2.2	ns
	tPHL	An to Bn or Bn to An	VCC = 5V	1.8
	CIN	Input capacitance (Control pins)	VI = 0V or VCC	3	pF
	CI/O	I/O pin capacitance	Outputs disabled; VI/O = 0V or VCC	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs low; VCC = 5.5V	9	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16501A DL	BT16501A DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16501A DGG	BT16501A DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16501A DL	BH16501A DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16501A DGG	BH16501A DGG	SOT364-1

1998 Feb 27

2

853-1788 19027

	Philips Semiconductors	Product specification
	18-bit universal bus transceiver (3-State)	74ABT16501A
		74ABTH16501A

LOGIC SYMBOL

					30		28 27				55		2		1
52																	5
			B1		CPBA		OEBA LEBA				CPAB		LEAB		OEAB A1
54			B0													A0		3
51			B2													A2		6
49			B3													A3		8
48			B4													A4		9
47			B5													A5		10
45			B6													A6		12
44			B7													A7		13
43			B8													A8		14
42			B9													A9		15
41			B10													A10		16
40			B11													A11		17
38			B12													A12		19
37			B13													A13		20
36			B14													A14		21
34			B15													A15		23
33			B16													A16		24
31			B17													A17		26
																	SA00127
PIN DESCRIPTION
PIN NUMBER					SYMBOL										NAME AND FUNCTION
1							OEAB								A-to-B Output enable input
27															B-to-A Output enable input
							OEBA
																	(active low)
2, 28				LEAB/LEBA												A-to-B/B-to-A Latch
																	enable input
55,30						CPAB/									A-to-B/B-to-A Clock input
							CPBA									(active rising edge)
3, 5, 6, 8, 9, 10, 12,																Data inputs/outputs
13, 14, 15, 16, 17,						A0-A17
																	(A side)
19, 20, 21, 23, 24, 26
54, 52, 51, 49, 48,
47, 45, 44, 43, 42,						B0-B17										Data inputs/outputs
41, 40, 38, 37, 36,																	(B side)
34, 33, 31
4, 11, 18, 25, 32, 39,							GND										Ground (0V)
46, 53
7, 22, 35, 50							VCC									Positive supply voltage

PIN CONFIGURATION

	OEAB
			1		56		GND
	LEAB
			2		55		CPAB
	A0
			3		54		B0
	GND		4		53		GND
							B1
	A1		5		52
	A2		6		51		B2
	VCC		7		50		VCC
	A3		8		49		B3
	A4		9		48		B4
	A5		10		47		B5
	GND		11		46		GND
	A6		12		45		B6
	A7		13		44		B7
	A8		14		43		B8
	A9		15		42		B9
	A10		16		41		B10
	A11		17		40		B11
	GND		18		39		GND
	A12		19		38		B12
	A13		20		37		B13
	A14		21		36		B14
	VCC		22		35		VCC
	A15		23		34		B15
	A16		24		33		B16
	GND		25		32		GND
	A17		26		31		B17
			27		30		CPBA
	OEBA
	LEBA		28		29		GND
						SA00128

1998 Feb 27

3

Philips Semiconductors Product specification

	18-bit universal bus transceiver (3-State)	74ABT16501A
		74ABTH16501A
	LOGIC SYMBOL (IEEE/IEC)

	OEAB	1
	CPAB	55
	LEAB	2
		27
	OEBA
	CPBA	30
	LEBA	28
	A0	3
	A1	5
	A2	6
	A3	8
	A4	9
	A5	10
	A6	12
	A7	13
	A8	14
	A9	15
	A10	16
	A11	17
	A12	19
	A13	20
	A14	21
	A15	23
	A16	24
	A17	26

EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D	1	1	54	B0
4	1	6D
			52	B1
			51	B2
			49	B3
			48	B4
			47	B5
			45	B6
			44	B7
			43	B8
			42	B9
			41	B10
			40	B11
			38	B12
			37	B13
			36	B14
			34	B15
			33	B16
			31	B17
				SA00129

1998 Feb 27

4