Philips 74ABTH16500CDL, 74ABTH16500CDGG, 74ABT16500CDL, 74ABT16500CDGG Datasheet

INTEGRATED CIRCUITS

74ABT16500C

74ABTH16500C

18-bit universal bus transceiver (3-State)

Product specification

1998 Feb 27

Supersedes data of 1997 Jun 12

IC23 Data Handbook

m n r

	Philips Semiconductors	Product specification
	18-bit universal bus transceiver (3-State)	74ABT16500C
		74ABTH16500C

FEATURES

•18-bit bidirectional bus interface

•3-State buffers

•74ABTH16500C incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Negative edge-triggered clock inputs

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

•Flexible operation permits 18 embedded D-type latches or flip-flops to operate in clocked, transparent, or latched modes.

DESCRIPTION

The 74ABT16500C is a high-performance BiCMOS Device which combines low static and dynamic power dissipation with high speed and high output drive.

This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low).

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Two options are available, 74ABT16500C which does not have the bus-hold feature and 74ABTH16500C which incorporates the bus-hold feature.

QUICK REFERENCE DATA

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL	UNIT
			Tamb = 25°C; GND = 0V
	tPLH	Propagation delay	CL = 50pF;	2.1	ns
	tPHL	An to Bn or Bn to An	VCC = 5V	1.7
	CIN	Input capacitance (Control pins)	VI = 0V or VCC	3	pF
	CI/O	I/O pin capacitance	Outputs disabled; VI/O = 0V or VCC	7	pF
	ICCZ	Quiescent supply current	Outputs disabled; VCC = 5.5V	500	μA
	ICCL		Outputs low; VCC = 5.5V	8	mA

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DWG NUMBER
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABT16500C DL	BT16500C DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABT16500C DGG	BT16500C DGG	SOT364-1
56-Pin Plastic SSOP Type III	±40°C to +85°C	74ABTH16500C DL	BH16500C DL	SOT371-1
56-Pin Plastic TSSOP Type II	±40°C to +85°C	74ABTH16500C DGG	BH16500C DGG	SOT364-1

1998 Feb 27

2

853-1800 19027

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)																																													74ABT16500C
																																											74ABTH16500C
LOGIC SYMBOL
					3		5		6		8		9		10		12		13		14		15		16		17		19		20		21				23			24		26
					A0		A1		A2		A3		A4		A5		A6		A7		A8		A9		A10		A11		A12		A13		A14				A15			A16		A17
			1		OEAB
			2		LEAB
			55		CPAB
			27		OEBA
			28		LEBA
			30		CPBA
					B0		B1		B2		B3		B4		B5		B6		B7		B8		B9		B10		B11		B12		B13		B14				B15			B16		B17
					54		52		51		49		48		47		45		44		43		42		41		40		38		37		36				34			33		31
																																									SA00322
PIN CONFIGURATION																							LOGIC SYMBOL (IEEE/IEC)
	OEAB		1				56		GND																					1
	LEAB		2																																			EN1
							55		CPAB
																													55
	A0		3				54		B0																														2C3
	GND		4				53		GND																				2									C3
	A1		5				52		B1																													G2
	A2		6				51		B2																				27									EN4
	VCC		7				50		VCC																					30									5C6
																													28
	A3		8				49		B3																													C6
	A4		9				48		B4																													G5
	A5		10				47		B5																					3																	54
																																					3D					1		1
	GND		11				46		GND
																																					4					1		6D
	A6		12				45		B6
																														5																	52
	A7		13				44		B7																					6																	51
	A8		14				43		B8																					8																	49
	A9		15				42		B9																					9																	48
	A10		16				41		B10																					10																	47
	A11		17				40		B11																					12																	45
	GND		18				39		GND																					13																	44
	A12		19				38		B12																					14																	43
	A13		20				37		B13																					15																	42
	A14		21				36		B14																				16																		41
	VCC		22				35		VCC																					17																	40
																													19																		38
	A15		23				34		B15
	A16		24				33		B16																					20																	37
	GND		25				32		GND																					21																	36
	A17		26				31		B17																					23																	34
																														24																	33
OEBA			27				30		CPBA
																													26																		31
LEBA			28				29		GND
							SW00035																																									SH00087

1998 Feb 27

3

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

74ABT16500C

74ABTH16500C

PIN DESCRIPTION

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1

OEAB

A-to-B Output enable input

27

B-to-A Output enable input (active low)

OEBA

2, 28

LEAB/LEBA

A-to-B/B-to-A Latch enable input

55,30

A-to-B/B-to-A Clock input (active falling edge)

CPAB/CPBA

3, 5, 6, 8, 9, 10, 12, 13, 14, 15,

A0-A17

Data inputs/outputs (A side)

16, 17, 19, 20, 21, 23, 24, 26

54, 52, 51, 49, 48, 47, 45, 44, 43,

B0-B17

Data inputs/outputs (B side)

42, 41, 40, 38, 37, 36, 34, 33, 31

4, 11, 18, 25, 32, 39, 46, 53

GND

Ground (0V)

7, 22, 35, 50

VCC

Positive supply voltage

FUNCTION TABLE

INPUTS

Internal

OUTPUTS

OPERATING MODE

Registers

OEAB

LEAB

CPAB

An

Bn

L

H

X

X

X

Z

Disabled

L

↓

X

h

H

Z

Disabled, Latch data

L

↓

X

I

L

Z

L

L

H or L

X

NC

Z

Disabled, Hold data

L

L

↓

h

H

Z

Disabled, Clock data

L

L

↓

I

L

Z

H

H

X

H

H

H

Transparent

H

H

X

L

L

L

H

↓

X

h

H

H

Latch data & display

H

↓

X

I

L

L

H

L

↓

h

H

H

Clock data & display

H

L

↓

I

L

L

H

L

H or L

X

H

H

Hold data & display

H

L

H or L

X

L

L

NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.

H = High voltage level

h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level

I = Low voltage level one set-up time prior to the Enable or Clock transition NC= No Change

X = Don't care

Z = High Impedance ªoff º state

↓ = High-to-Low Enable or Clock transition

1998 Feb 27

4