Philips 74abt h16500c DATASHEETS

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74ABT16500C
74ABTH16500C

18-bit universal bus transceiver (3-State)

Product specification
Supersedes data of 1997 Jun 12
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent su ly current

18-bit universal bus transceiver (3-State)

FEA TURES

•18-bit bidirectional bus interface

•3-State buffers

•74ABTH16500C incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Output capability: +64mA/-32mA

•TTL input and output switching levels

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•Negative edge-triggered clock inputs

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

•Flexible operation permits 18 embedded D-type latches or

flip-flops to operate in clocked, transparent, or latched modes.

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

C
C
I

CCZ

I

CCL

IN

I/O

Propagation delay
An to Bn or Bn to An

Input capacitance (Control pins) VI = 0V or V
I/O pin capacitance Outputs disabled; V

pp

CL = 50pF;
VCC = 5V

Outputs disabled; VCC = 5.5V 500 µA
Outputs low; VCC = 5.5V 8 mA

74ABT16500C

74ABTH16500C

DESCRIPTION

The 74ABT16500C is a high-performance BiCMOS Device which
combines low static and dynamic power dissipation with high speed
and high output drive.

This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA

), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA
LEBA and CPBA
active High, and OEBA is active Low).

Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.

Two options are available, 74ABT16500C which does not have the
bus-hold feature and 74ABTH16500C which incorporates the
bus-hold feature.

CONDITIONS

T

= 25°C; GND = 0V

amb

CC

. The output enables are complimentary (OEAB is

TYPICAL UNIT

2.1

1.7
3 pF

= 0V or V

I/O

CC

7 pF

,

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16500C DL BT16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16500C DGG BT16500C DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16500C DL BH16500C DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16500C DGG BH16500C DGG SOT364-1

1998 Feb 27 853-1800 19027

2

Philips Semiconductors Product specification

18-bit universal bus transceiver (3-State)

LOGIC SYMBOL

3 5 6 8 9 10121314151617192021232426

A0 A1 A2 A3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17A4

OEAB

1

LEAB

2

CPAB

55

OEBA

27

LEBA

28

CPBA

30

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17

54 52 51 49 47 45 44 43 42 41 40 38 37 36 34 33 3148

PIN CONFIGURA TION

74ABT16500C

74ABTH16500C

SA00322

LOGIC SYMBOL (IEEE/IEC)

OEAB

1

LEAB

2

A0

3

GND

4

A1

5

A2

6
7

V

CC

A3

8

A4

9

A5

10
11

GND

A6

12

A7

13

A8

14

A9

15

A10

16

A11

17
18

GND GND

A12

19

A13

20

A14

21
22

V

CC

A15

23

A16

24
25

GND

A17

26
27

OEBA

28 29

LEBA

56

GND
CPAB

55
54

B0

53

GND

52

B1

51

B2

50

V

49

B3

48

B4

47

B5

46

GND

45

B6

44

B7

43

B8

42

B9

41

B10

40

B11
39
38

B12
37

B13
36

B14
35

V
34

B15
33

B16
32

GND
31

B17
30

CPBA

GND

CC

CC

1
55
2

27
30
28

3

5
6
8

9
10
12

13
14
15

16
17
19
20
21
23
24
26

EN1

2C3
C3
G2
EN4

5C6
C6
G5

3D 1 1
416D

54

52
51
49
48

47
45
44
43
42
41
40
38
37
36
34
33
31

1998 Feb 27

SW00035

SH00087

3

Philips Semiconductors Product specification

Disabled, Latch data

Disabled, Clock data

Transparent

Latch data & displa

Clock data & displa

Hold data & displa

18-bit universal bus transceiver (3-State)

74ABTH16500C

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1 OEAB A-to-B Output enable input

27 OEBA B-to-A Output enable input (active low)

2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input

55,30 CPAB/CPBA A-to-B/B-to-A Clock input (active falling edge)

3, 5, 6, 8, 9, 10, 12, 13, 14, 15,

16, 17, 19, 20, 21, 23, 24, 26

54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

FUNCTION TABLE

INPUTS

OEAB LEAB CPAB An

L H X X X Z Disabled
L ↓ X h H Z
L ↓ X I L Z
L L H or L X NC Z Disabled, Hold data
L L ↓ h H Z

L L ↓ I L Z
H H X H H H
H H X L L L
H ↓ X h H H
H ↓ X I L L
H L ↓ h H H
H L ↓ I L L
H L H or L X H H
H L H or L X L L

NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level

h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance “off” state
↓ = High-to-Low Enable or Clock transition

A0-A17 Data inputs/outputs (A side)

B0-B17 Data inputs/outputs (B side)

CC

Positive supply voltage

Internal

Registers

OUTPUTS

Bn

OPERATING MODE

74ABT16500C

p

p

y

p

y

p

y

1998 Feb 27

4